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Arithmetic shift left overflow:

For shift left operations the overflow condition needs to be decided based on the following check:

Amsb and Amsb-1 are two MSB bits of the register.

For shift left operations the overflow condition needs to be decided based on the following check:

Amsb and Amsb-

Arithmetic shift microoperations

In this operation we shift signed binary numbers left or right. For these operations proper care must be taken. Lets discuss this shift operation in three sections.

Arithmetic shift right:

Arithmetic shift left:

Arithmetic shift left overflow:

In this operation we shift signed binary numbers left or right. For these operations proper care must be taken. Lets discuss this shift operation in three sections.

Arithmetic shift right:

Arithmetic shift left:

Arithmetic shift left overflow:

Discussion on Arithmetic shift microoperations -

Arithmetic shift right:

Shift right for signed numbers is same as dividing the bin number by 2.

Arithmetic shift left:

Shift left for signed numbers is same as multiplying the bin number by 2.

Arithmetic shift right:

Shift right for signed numbers is same as dividing the bin number by 2.

Arithmetic shift left:

Shift left for signed numbers is same as multiplying the bin number by 2.

Links to all microoperations discussion.

Arithmetic microoperations discussion,

Logical microoperations discussion,

Shift microoperations discussion,

Overflow conditions and discussion.

Arithmetic microoperations discussion,

Logical microoperations discussion,

Shift microoperations discussion,

Overflow conditions and discussion.

Verilog code examples for shift micro-operations are at links below:-

Logical Shift Right (LSR) verilog code,

Logical Shift left (LSL) verilog code,

Circular Shift Right (CSR) verilog code,

Circular Shift Left (CSL). Verilog code.

Logical Shift Right (LSR) verilog code,

Logical Shift left (LSL) verilog code,

Circular Shift Right (CSR) verilog code,

Circular Shift Left (CSL). Verilog code.

Interview Questions. Main, FPGA, Digital Fundamentals

The overflow is detected based on following equation.

Of = Amsb XOR Amsb-

If Of = 0 then no overflow detected.

Else overflow and a sign reversal needs to be done after left shift.

Resources

Verilog RTL code examples for front-end chip design.

Digital Design Topics

Half-adder , full-adder ,

Adder-sub tractor

Stack Organization - LIFO, RPN

Parity Generation and error checking

Binary multiplier circuit.

CMOS introduction

Digital fundamentals -

RTL coding guidelines. ICG cell, Assertions, $assertkill, levels. Chandle

Pipeline vs. Parallel processing.

Verilog RTL code examples for front-

Half-

Adder-

Stack Organization -

Binary multiplier circuit.

CMOS introduction

Digital fundamentals -

RTL coding guidelines. ICG cell, Assertions, $assertkill, levels. Chandle

Pipeline vs. Parallel processing.

Computer Organization.

Computer Introduction. Building blocks - ALU, ACC, PC, Registers, Stack Pointer, IR, timing and control unit.

Memory Organization.

Cache memory, fully-associative cache , hardware architecture, match circuit, control circuit. Direct-mapped cache , main memory and discussion.

Interrupt controller, Vectored Interrupt Controller. Interrupt registers

Computer Introduction. Building blocks -

Memory Organization.

Cache memory, fully-

Interrupt controller, Vectored Interrupt Controller. Interrupt registers

LTE - Long Term Evolution topics from here

5 Steps required to build a functional FPGA load (valid for most EDA flows)

How to implement a Integrated Clock Gating (ICG) cell from vendor library.

CMOS Digital Integrated Circuit design for VLSI.