﻿ Arithmetic shift microoperations. right left shit overflow
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Arithmetic shift left overflow:
For shift left operations the overflow condition needs to be decided based on the following check:

Amsb and Amsb-1 are two MSB bits of the register.
Clock Crossing Async FIFO Half Adder Full Adder Binary Adder Overflow Overflow Det Adder-Subtractor Multiplier Parity check RTL guidelines NAND to INVERTER VHDL RTL Arith Micro-ops Stack Org Parallel proc. Pipeline proc CMOS Intro
Arithmetic shift microoperations
In this operation we shift signed binary numbers left or right. For these operations proper care must be taken. Lets discuss this shift operation in three sections.
Arithmetic shift right:
Arithmetic shift left:
Arithmetic shift left overflow:
Discussion on Arithmetic shift microoperations -

Arithmetic shift right:
Shift right for signed numbers is same as dividing the bin number by 2.
Arithmetic shift left:
Shift left for signed numbers is same as multiplying the bin number by 2.
Links to all microoperations discussion.

Arithmetic microoperations discussion,
Logical microoperations discussion,
Shift microoperations discussion,
Overflow conditions and discussion.
Verilog code examples for shift micro-operations are at links below:-

Logical Shift Right (LSR) verilog code,
Logical Shift left (LSL) verilog code,
Circular Shift Right (CSR) verilog code,
Circular Shift Left (CSL). Verilog code.
Interview Questions. Main, FPGA, Digital Fundamentals

The overflow is detected based on following equation.

Of = Amsb XOR Amsb-1

If Of = 0 then no overflow detected.

Else overflow and a sign reversal needs to be done after left shift.

Resources

Verilog RTL code examples for front-end chip design.
Digital Design Topics
Stack Organization - LIFO, RPN
RTL coding guidelines. ICG cell, Assertions, , levelsChandle
Pipeline vs. Parallel processing.
LTE - Long Term Evolution topics from here

(valid for most EDA flows)

How to implement a(ICG) cell from vendor library.