Home.Verilog.Digital Design.Digital Basics.Python.RF Basics.
Previous.
Next.
Custom Search

Legal Disclaimer

Chip Designing for ASIC/ FPGA Design engineers and Students
FULLCHIPDESIGN
Digital-logic Design...  Dream for many students… start learning front-end…

Legal Disclaimer

@TYH :- 4G LTE Long Term Evolution Tutorial, CloudComputing
PICS
Verilog Tutorial.
Get Noticed:- Submit your own content to be published on fullchipdesign.com

Send it to fullchip@gmail.com

Digital Basics Tutorial.
Universal Bitwise operations - NAND, NOR and XNOR. Verilog code and test-bench  
Bitwise - Operation on individual bits of registers r1 and r2. Results are stored in register ‘acc’.
C:\iverilog\samples>..\bin\vvp step
************************************
******* Universal Bitwise NAND ********
Time=                   0 (Nano seconds)
ACC = 01
******* Universal Bitwise NOR *********
Time=                   5 (Nano seconds)
ACC = 00
****** Universal Bitwise XNOR ********
Time=                  25 (Nano seconds)
ACC = 10
Results for above program is shown below: AND NOR and XNOR .
C:\iverilog\samples\verilog_operators2.v.html module tb_opereators
(
);

reg[1:0] r1;
reg[1:0] r2;
reg[1:0] acc;

initial begin
        $display ("****************************");
        $monitor (" Time=%t\n ACC = %b", $time, acc);  
        r1 = 2'b10;
        r2 = 2'b11;
        /* universal NAND opeartion */
        acc = r1 ~& r2;
        $display ("******* Universal Bitwise NAND ***********");
        /* NOR */
        # 5 acc = r1 ~| r2;
        $display ("******* Universal Bitwise NOR ************");
#15 
        r1 = 2'b00;
        r2 = 2'b01;
        /* Bitwise XNOR */
        # 5 acc = r1 ~^ r2;
        $display ("****** Universal Bitwise XNOR **********");
        $finish;      
end

endmodule
Bitwise Universal
Interview Questions. Main, FPGA, Digital Fundamentals

In following verilog testbench code  corresponding bit of each register r1, r2 is individually operated for nand, nor or xnor logic and stored in corresponding bit position of acc register. This kind of operation is know as bitwise logic.

LTE Log Term Evolution topics from here

Guide to Graduate studies in USA.

Bitwise.

3D draw and render new, 2D, 2D to 3D, ARC, 3D semi-cylindrical,  door,  Edgeing, drawer, colors  and render.

Interview Questions. Main, FPGA, Digital Fundamentals