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Boolean Algebra

The duality property of Boolean algebra state that all binary expressions remain valid when following two steps are performed:

Step 1 : Interchange OR and AND operators.

Step 2 : Replace all 1’s by 0’s and 0’s by 1’s.

Adding a number to ‘0’ :

P1. Postulate:-

P2. Postulate:-

Sum of a number and its complement from a Set is ‘1’.

Digital Logic fundamentals topics @ fcd. Digital basics tutorial

Binary number discussion, 1 and 2 complement discussion, Binary arithmetic, Signed Magnitude, overflow, examples, Gray coding, Binary coded digital (BCD) coding, BCD addition

Digital logic gates basic (AND, OR, XOR, NOT) and derived (NAND, NOR and XNOR). Drive XOR from NAND gates. Drive XOR from NOR gates

Discussion of Boolean Algebra with examples.

Duality Principle, Huntington Postulates, Theorems of Boolean Algebra - discussion with examples,

Boolean Functions,

Canonical and Standard Forms, Minterms and Maxterms

Sum of Minterms, Product of Maxterms or Canonical Forms, Karnaugh map or K-map discussion 2, 3, ,4 and 5 var’s Prime Implicant and Gate level minimization

Binary number discussion, 1 and 2 complement discussion, Binary arithmetic, Signed Magnitude, overflow, examples, Gray coding, Binary coded digital (BCD) coding, BCD addition

Digital logic gates basic (AND, OR, XOR, NOT) and derived (NAND, NOR and XNOR). Drive XOR from NAND gates. Drive XOR from NOR gates

Discussion of Boolean Algebra with examples.

Duality Principle, Huntington Postulates, Theorems of Boolean Algebra -

Canonical and Standard Forms, Minterms and Maxterms

Sum of Minterms, Product of Maxterms or Canonical Forms, Karnaugh map or K-

P3. Postulate:-

P4. Postulate:-

From commutative property of binary numbers we have:-

P5. Postulate:-

From duality of P5

P6. Postulate:-

From distributive property of binary numbers we have:-

P7. Postulate:-

From duality of P7

Resources

Verilog RTL code examples for front-end chip design.

Digital Design Topics

Half-adder , full-adder ,

Adder-sub tractor

Stack Organization - LIFO, RPN

Parity Generation and error checking

Binary multiplier circuit.

CMOS introduction

Digital fundamentals -

RTL coding guidelines. ICG cell, Assertions, $assertkill, levels. Chandle

Pipeline vs. Parallel processing.

Verilog RTL code examples for front-

Half-

Adder-

Stack Organization -

Binary multiplier circuit.

CMOS introduction

Digital fundamentals -

RTL coding guidelines. ICG cell, Assertions, $assertkill, levels. Chandle

Pipeline vs. Parallel processing.

Solved Examples for 3 variable Kmaps

1. F(x,y,z) = (0,1,6,7) - Minimization, on this page.

2. F(x,y,z) = (0,1,4,5,6,7) - Minimization from here.

3. F(x,y,z) = (3,4,6,7) - Minimization from here.

4. F(x,y,z) = (0,1,2,3,4,5,6,7) - Minimization from here.

1. F(x,y,z) = (0,1,6,7) -

4G LTE - Long Term Evolution topics from here