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CMOS digital ASIC’s design process and Parasitics
CMOS IC design Process
CMOS is a Digital Integrated Circuit design process for Very large scale productions. The compact term for the process is CMOS VLSI (Very Large Scale Implementation).

This design flow is a custom flow targeted specifically for mass production of IC’s for various applications. The compact term for the flow is ASIC (Application specific Integrated circuits)

Some example’s of CMOS IC’s from the industry are:
1. Application processor’s for smart phones.
2. Base band ASIC’s for phones (CDMA, EVO, GSM or WiMax).
3. Chipset's for controlling automobiles automated functions.
4. Image processing ASIC’s for digital TV’s (LCD or Plasma Etc). Etc.
The CMOS circuit design process mainly involves following steps
1. Design Specifications.

2. Logic design, synthesis and timing analysis (with targeted layout libraries.) The final output of this process is a gate-level netlist. This step is also know as front-end design flow.  

3. Translate gate level circuit into a layout primarily using CMOS cells.

4. Use the layout’s from step 3 to calculate initial performance parasitic’s using circuit extraction program’s.

5. Run simulations using parasitic's from step 4. Compare the results with step 1.

6. Optimize the circuit in step 3 using results from step 5 to achieve step 1.

7. Fabricate and test the circuit in step 3.
CMOS Parasitics
A custom layout of any ASIC requires intensive knowledge of the parasitics involved.

Parasitics are listed below:-
1. Stray capacitances and leakage problems associated with it.
2. Mutual Inductances and problems with unwanted coupling between conductors.
3. Resistance's.
4. PN junctions.
5. Bipolar transistors.

Crosstalk discussion.
Ground Bounce discussion.



Ground bounce.