Home Verilog Digital Design Digital Basics Python RF Basics

Legal Disclaimer

Chip Designing for ASIC/ FPGA Design engineers and Students
Digital-logic Design...  Dream for many students… start learning front-end…
Topics @TYH :- 4G LTE Tutorial, GVIM editor, Smart-Phone, Cloud Computing
Custom Search

Feedback ? Send it to admin@fullchipdesign.com or join me at fullchip@gmail.com

Legal Disclaimer

Shim Events, Trans Logic Values Signals
Verilog Tutorial.
Digital Basics Tutorial.
Events, transaction, propagation delays and concurrence
Lets start our discussion with an example of half-adder circuit. Half-adder circuit shown below has 3 inputs (x, y and carry_in) and 2 outputs (sum and carry_out). This circuit computes sum of two bits and reports carry.
Event - Whenever there is a change at input there is a corresponding change at the output. This change is know as an “event” in digital circuit design and analysis.

Transaction - Its not necessary that a change at input will result in an output change. This scenario is know as transaction.

Before we go any forward, lets discuss more about physical layout of digital circuits. -
The physical design primarily consists of devices like transistors, wire and noise canceling circuits. The transistors can itself be laid out in various structures to create logic gates , flip-flops etc.

Propagation Delay - Whenever a change is applied at the input of a circuit there is an associated delay or resistance in the path. This period of time is known as Propagation delay. These delays are also know as inertial delays and their values are directly proportional to the length of wire.
Half -Adder Circuit
Concurrent Operations in digital circuits:
Whenever two different signals change values due to change in any one or more inputs are a result of concurrency in digital circuit. In our example change in any one input can result in a different value at the output. Refer Truth-table below.
Truth table for Half-adder circuit is shown below:
From the truth-table enclosed in dotted box above:

Event: Input_y transitioning from 0 to 1.

Concurrent operation results:
Output_sum going from 1 to 0
Output_carry going from 0 to 1.

Effect of Propagation Delay:
The outputs Sum and Carry may not change
Verilog Tutorial Topics @ fullchipdesign.
Interview Questions. Main, FPGA, Digital Fundamentals
LTE - Long Term Evolution topics from