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Asynchronous FIFO design and calculate the Depth of the FIFO

Understanding FIFO design requirements

FIFO is a First in First Out is used to buffer data in Digital Systems. Requirement of FIFO arises when the reads are slower than the writes.

Designing a FIFO

Calculating FIFO parameters:

In order to calculate the depth of the FIFO, first we need to understand the worst case scenario of that particular design.  Here is an example of a worst case scenario:- example below

Write side of FIFO:

Write clock frequency = 15 MHz (clk_wr)

Maximum size of the Burst = 100 bytes (burst_width)

Delay between writes in a burst = 1 clock cycle (wr_delay)

 

Read side of FIFO

Read clock Frequency = 10 MHz (clk_read)

Delay between reads = 2 clock cycles (rd_delay)

 

Six step approach to calculate FIFO parameters.

Step1:- FIFO Width = 8 (1 byte = 8 bits worth of data at each buffer location)

Step2:- Assume depth of FIFO to capture the complete buffer = 100 (maximum size of burst)

Step3:- No of write clock cycles for writing 100 locations in FIFO = 100 @ clk_wr

Step4:- Time taken to write 100 locations = 100/(15*10^6) = 6.67 us

Step5:- No of reads during 6.67 us = (6.67 us) * 10 * 10^6 = 66.7 @ clk_read (approx 67)

Step6:- No of dead cycles between reads = 2

Depth of the FIFO = 100 – 66.7/2 = 100 – 33.35 = 66.65 = 67

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