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Verilog Tutorial.
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Digital Basics Tutorial.
Step 1 - Synthesis
Synthesize all the RTL source code using one of industry standard tools to create a database of nets, gates, RAM’s, LUT’s (Look Up Table’s - most common for FPGA’s) that layout tools can read.
5 Steps required to build a functional FPGA load (valid for most EDA flows)
Step 3 - Constraints file
Write a constraints file to do define rules for EDA flow :-

Step 4 - Place and Route


Import synthesized netlist into Place and Route (Layout) tool to do actual floor-plan static timing analysis and gate level layout of synthesized (step 1) netlist.

Step 5 - Static Timing Analysis


The most important step is to analyzed the final netlist against the constraints specified in Step3. In this step we look for setup time violations, hold time violations. The reports with significant timing violations needs to be carefully analyzed and necessary changes needs to be incorporated in designs.  

Step 2 - Layout/Device Pin-map

Write a pin file to map RTL top-level Inputs/Outputs to fpga physical pins. Also set correct drive strengths, voltages for the IO’s.

FPGA Interview questions.
Digital Interview Questions.


Parameters passing, defparam & localparam

Alias, Array, Assertions


LTE - Long Term Evolution topics from here

Create clocks and set frequencies in terms of periods (1/f).

Define generated clocks, mostly divided clocks from PLL output’s. Resets and associated constraints (like false path). Set false path between asynchronous logic.

Define multi-cycle paths etc.


5 Steps required to build a functional FPGA load (valid for most EDA flows)

How to implement a Integrated Clock Gating (ICG) cell from vendor library.

CMOS Digital Integrated Circuit design for VLSI.