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Chip Designing for ASIC/ FPGA Design engineers and Students
Digital-logic Design...  Dream for many students… start learning front-end…

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Verilog Tutorial.
Digital Basics Tutorial.
~\Desktop\FCD\temp\temp.v.txt.html // Full Adder rtl

module full_adder
(in_x, in_y, carry_in, sum_out,
input  in_x;
input  in_y;
input  carry_in;
output sum_out;
output carry_out;

wire w_sum1;
wire w_carry1;
wire w_carry2;

assign carry_out = w_carry1 | w_carry2;

// Instantiate two half-adders to make the circuit. Click here for half-adder rtl

half_adder u1_half_adder
half_adder u2_half_adder

Full-Adder discussion with verilog rtl and testbench
Verilog RTL example for full-adder. Check the half-adder and full-adder discussion in digital design

Checkout verilog test-bench code to validate full-adder design.

Final results from the test-bench are shown below.

Interview Questions. Main, FPGA, Digital Fundamentals
Half-adder.Tristate buffer.

Full Adder Block Diagram: A critical building block in logic design. Discussion from here.

INTERVIEW Questions: Start early in your Job interview preparations

How do you represent Universal NAND Gate.

Derive AND gate by using only NAND gates.

Derive OR gate by using only universal NAND gates.

Derive XOR gate by only using NAND gates. Discuss with truth -table.