Diagram to show routing of data across FPGA’s and requirements for doing Static Timing
Guideline 4:-Implementing clock domain crossing is the most complicated design scenario
in digital circuits. Necessary steps to design involves detailed analysis of the
clocks across the domain.
Following are some ideas to implement clock domain crossing: Use rate – change FIFO,
Double clocking, Gray encoders for counters.
Guideline 5:-Wires and Registers should be correctly implemented in Verilog. Registers
must be used within always blocks. Wires are used for connectivity outside always
blocks and are generally used with assign statements or for connectivity not requiring
any registered delay.
Guideline 6:Blocking vs. non-blocking stms.
Blocking statements are always used within combinatory block to execute statements
in a sequence. Non – blocking statements are always executed in a sequential logic
block to execute all statements in at either clock edge.
Guideline 7:Never mix blocking and non-blocking stms in a single always block in
RTL Coding guidelines for ASIC/FPGA implementations
Guideline 1:-Declare every possible state in conditional statements. Missing a declaration
can result in un-intentional latches in design.
if (condition True)
d_ff <= ’b1;
d_ff <= ‘b0;
Guideline 2:-All the signals coming to/from external world should be properly registered
to avoid setup time violations.
Guideline 9:-After simulating the design, always synthesize it and check for latches,
unbounded component, tri-state logic etc.
Guideline 10: -Conditional IF statements should not be used in parallel states.
Case statements best
Guideline 8:-Suggested approach to write synthesizable RTL is to separate the synchronous
and combinational logic into separate processes (always blocks in Verilog).