Home Verilog Digital Design Digital Basics Python RF Basics

Legal Disclaimer

Chip Designing for ASIC/ FPGA Design engineers and Students
FULLCHIPDESIGN
Digital-logic Design...  Dream for many students… start learning front-end…
Custom Search

Feedback ? Send it to admin@fullchipdesign.com or join me at fullchip@gmail.com

Verilog Initial stmts IF-ELSE Case stms Readmemh Function Testbench Binary to Gray Clock Crossing Half-adder Full-adder Tristate buffer Adder tb Counter_enable Blocking Operators Shift LSR Random Nos Sync RAM Verilog Tutorial

Legal Disclaimer

Topics @TYH :- 4G LTE Tutorial, GVIM editor, Smart-Phone, Cloud Computing
Previous Next
Verilog Tutorial.
Digital Basics Tutorial.
Half-Adder discussion with verilog rtl and testbench
Verilog RTL example for half-adder. Check the half-adder discussion in digital design section.

// Half Adder

module half_adder (in_x, in_y, out_sum, out_carry);

input  in_x;

input  in_y;

output out_sum;

output out_carry;

assign out_sum = in_x^in_y;

assign out_carry = in_x&in_y;

endmodule

Results:

1 Bit Half-Adder Results are discussed below

in_x = 0, in_y = 0, out_sum = 0, out_carry = 0

in_x = 0, in_y = 1, out_sum = 1, out_carry = 0

in_x = 1, in_y = 1, out_sum = 0, out_carry = 1

in_x = 1, in_y = 0, out_sum = 1, out_carry = 0

in_x = 1, in_y = 1, out_sum = 0, out_carry = 1

in_x = 0, in_y = 1, out_sum = 1, out_carry = 0

Half- adder test-bench code can be referred from here. Further topics full-adder, 4-bit binary adder, 4-bit binary adder-subtractor.
Other sections of interest on FCD
Interview Questions. Main, FPGA, Digital Fundamentals