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Digital Basics Tutorial.
How to implement a Integrated Clock Gating (ICG) cell from vendor library.
Most of  ICG module instances will possibly have following IO’s
3 input ports -  clk, clk_en and test
1 output port - clk for gated clock.
Automated Insertion of ICG -
Some power aware tools insert the ICG’s through automated software algorithms.
Most common types of common clock gating cells are listed below

Latch Based Clock Gating Buffer for Negedge.
Latch Based Clock Gating Buffer for Posedge.
Latch Based Clock Gating Buffer Posedge diagram -  The circuit employs a latch with inverted clock input and a AND gate. The output clock is always clock gated HIGH when Enable is low.
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On this page Integrated Clock Gating (ICG) cell
Interview Questions. Main, FPGA, Digital Fundamentals

Latch Based Clock Gating Buffer Negedge diagram -  The circuit employs a latch and OR gate with one input inverted. The output clock is always clock gated low when Enable is low.

Purpose - During idle modes, the clocks can be gated-off to save dynamic power dissipation on flip-flops. Proper circuit is essential to achieve a gated clock state to prevent false glitches on clock path.

 

Technique - Use a combination of AND and a Latch  to avoid any glitches on the clocks. A glitch can propagate a false edge on to the design.

 

Manual insertion of ICG - The clock gating can be implemented through logic circuits and ICG’s. Most of Clock Gating Cells from vendor libraries have a Verilog or VHDL rtl codes. The Verilog versions has module instance that can be instantiated in the source code.

Assertions.

SystemVerilog

Parameters passing, defparam & localparam

Alias, Array, Assertions

 

LTE - Long Term Evolution topics from here
Assertions.