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Digital-logic Design...  Dream for many students… start learning front-end…
Topics @TYH :- 4G LTE Tutorial, GVIM editor,

Digital Logic

Q. Give two ways of converting a two input NAND gate to an inverter. Hint:

Q. How to calculate depth of  FIFO for rate change implementation ? Answer: FIFO design example

Q. Simplify Boolean Functions F = xyz + x’y + xyz’. Answer: Q. Represent F = x + yz + xy in Sum of Product terms. Q. Represent F = x + yz + xy in Product of Sum terms. Answer

Q. What do you mean by prime Implicants? What are Essential Terms ? Why it is required ? Click here

Q. Consider a function F (x, y, z, w) of 11 Minterms shown in Gate level minimization

Q. How do you represent Universal NAND Gate.

Q. Derive AND gate by using only NAND gates.

Q. Derive OR gate by using only universal NAND gates.

Q. Derive XOR gate by only using NAND gates. Discuss with truth -table. More digital basics interview questions for entry-level jobs. Click here

Q. Do you understand Pipeline Architecture? Differentiate it from Parallel processing. Most important design question for most interviews.

Static Timing Analysis

Q. Setup time and hold time in digital circuits. ? Hint : Access from here

Q. False path in FPGA’s, Critical path, Negative slack, Jitter vs. clock skew .

Q. Routing delay, Flop to out delay, Flop to flop delay, Pad to flop delay, Board delay.

Q. Knowledge of Synthesis and layout constraints.

Getting through interviews is always a challenging task and requires thorough preparation. Here is a list of probable questions that may appear in an interview related to RTL skills. Three areas are covered Digital Design, Digital Fundamentals and FPGA Design.
RTL or Register Transfer Level Logic Design Questions
Q. How do you differentiate between coding in C/C++ and at RTL (Register Transfer Level) ? Hint: In RTL logic is divided into sequential and combinational logic blocks.
Q. How do you differentiate between wires and registers in Verilog ?Hint: Registers are used to store values and wires are used only for connections. D Flip-flops in Digital design generally represents registers.
Q. How do you diff between blocking vs. non-blocking statements in Verilog ? Click here
Q. Sensitivity lists declaration in always block for sequential and combinational logic?
Q. Differentiate between tasks and functions in Verilog?
Q. When the latches are inferred in RTL ? Hint : click here
Q. How to differentiate between ‘==‘ and ‘= = =‘ logic? Hint : ’===’ are not synthesizable & used in simulations.
Q What are assertions in digital logic design?
Q Can you describe Verilog parameters and parameter passing? Hint: click here
Q how do you define Events, transaction, propagation delays and concurrence?
Q What is constant propagation for logic during synthesis? Direct link
Q. How to generate clocks on FPGA? Hint : Should use Digital Clock Manager’s for clock generations.
Q. Gated clocks in FPGA implementations ? Hint:  No gated clocks in FPGA implementations.
Q. Which part of the fpga flow you specify the clock frequency for the design?
Hint:- Both synthesis and layout.
Q. How to constrain clock crossing paths in design? Hint:- False path it. No need to specify timing information for these paths.
Q. How do you synchronize counters in async-fifo design with different read/write clocks.? Hint: use gray coding, Binary to gray
Digital Logic fundamentals -
Digital basics tutorial : - Binary number discussion, 1 and 2 complement discussion, Binary arithmetic, Signed Magnitude discussion with examples, Gray coding, Binary coded digital (BCD) coding, BCD addition, Digital logic gates basic (AND, OR, XOR, NOT) and derived (NAND, NOR and XNOR), Discussion of Boolean Algebra with examples, Duality Principle, Huntington Postulates, Theorems of Boolean Algebra - discussion with examples, Boolean Functions, Canonical and Standard Forms, Minterms and Maxterms, Sum of Minterms, Product of Maxterms or Canonical Forms, Karnaugh map or K-map discussion 2, 3, ,4 and 5 var’s, Prime Implicant and Gate level minimization examples.
LTE - Long Term Evolution topics from here
Resources
Verilog RTL code examples for front-end chip design.
Digital Design Topics
Stack Organization - LIFO, RPN
RTL coding guidelines. ICG cell, Assertions, , levelsChandle
Pipeline vs. Parallel processing.
Interview Questions. Main, FPGA, Digital Fundamentals
How do you represent Universal NAND Gate.
Derive AND gate by using only NAND gates.
Derive OR gate by using only universal NAND gates. Derive XOR gate by only using NAND gates. Discuss with truth -table.
LTE - Long Term Evolution topics

Miscellaneous

Q. Do you understand Parity generation and checking for digital communication?

Q. How to use signed magnitude in Verilog? Hint: access verilog code. Also refer signed magnitude logic.

FPGA - Field Programmable Gate Array related interview Questions.

Misc. Verilog RTL examples:-

Carry_out
Do you know
what circuit

Behavioral

Q. How will you allocate your time between architecture, coding, and verification?

Q. Checkout the company web pages and on search engines about the latest technology and products.

Q. Prepare a  set of questions to ask the interviewer about the group and or company.

Finally … relax and chill out for few hours before the interview.

INTERVIEW Questions: Start early in your Job interview preparations
How do you represent Universal NAND Gate.
Derive AND gate by using only NAND gates.
Derive OR gate by using only universal NAND gates.
Derive XOR gate by only using NAND gates. Discuss with truth -table.