Chip Designing for ASIC/ FPGA Design engineers and Students
Digital-logic Design... Dream for many students… start learning front-end…
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Any adjacent 2, 4 or 8 cells can be grouped to find a minimized logic value. Following plot will show grouping of adjacent cells.
F = x’y’(z+z’) + xy(z+z’)
F= x’y’ + xy .. Final Answer.
Clock Domain Crossing
rtl & testbench example.
Rate change (asynchronous) FIFO design and fifo depth calculation.
Half-adder, Full-adder, 4-bit binary adder , adder-subtractor circuit, overflow with rtl & testbench. Binary Multiplier, Parity error TT Arithmetic, logical, shift micro-operations. Stack organization, LIFO, RPN discussion.
VHDL rtl - Synchronous flip-flop, latch, shim to improve timing and counter example
RTL coding guidelines. ICG cell, Assertions, $assertkill, levels.
Digital design Interview questions.
FPGA Interview. FPGA flow. Graduate studies in US. Pipeline vs. Parallel processing.
1. F(x,y,z) = (0,1,6,7) - Minimization, discussed on this page.
2. F(x,y,z) = (0,1,4,5,6,7) - Access minimization from here.
3. F(x,y,z) = (3,4,6,7) - Access minimization from here.
4. F(x,y,z) = (0,1,2,3,4,5,6,7) - Access minimization from here.
Following list of functions are minimized using 3 var K-map’s.
The K-map for 3 variables is plotted above. You will notice the column for 11 and 10 is inter-changed. This is done to allow only one variable to change across adjacent cells. This adjustment in columns allows in minimization of logic mapped into tables.
The two step minimization equation is shown below.
With reference to the table above the cells under the dotted box’s can be combined to come-up with following reduced equation.
LTE - Long Term Evolution topics