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Karnaugh map or K-

2,3,4,5 variables K-

Following k-

First write the Truth Table for 2 variables x and y. Once we know all the values
in table its easier to plot the 2 var k-

2 variable K– map plot below : -

K-map location number

x

y

Output function

0

0

0

x’y’

1

0

1

x’y

2

1

0

xy’

3

1

1

xy

0

1

0

1

x

y

x’y’

x’y

xy’

xy

Misc. Verilog RTL examples:-

Binary to Gray Code conversion, File read write operations. Clock domain crossing., Half-adder , Full-adder , Tri-state buffer , Verilog testbench to validate half-adder, full-adder and tri-state buffer.

2 variable solved k-

A solved example of 2 variable k-

F(x,y)=sum(0,2,3)

Minimization solution to above function.

= y’(x + x’) + xy + xy’ = y’ + x (y+y’) = y’ + x

K-

0

1

0

1

x

y

x’y’ =1

xy’ = 1

xy = 1

Interview Questions. Main, FPGA, Digital Fundamentals

Computer Organization.

Computer Introduction. Building blocks - ALU, ACC, PC, Registers, Stack Pointer, IR, timing and control unit.

Memory Organization.

Cache memory, fully-associative cache , hardware architecture, match circuit, control circuit. Direct-mapped cache , main memory and discussion.

Interrupt controller, Vectored Interrupt Controller. Interrupt registers

Computer Introduction. Building blocks -

Memory Organization.

Cache memory, fully-

Interrupt controller, Vectored Interrupt Controller. Interrupt registers

LTE - Long Term Evolution topics from here

Universal NAND Gate.

Derive AND gate from NAND gate.

Derive OR gate from NAND gate

Derive XOR gate from NAND gate.

Derive AND gate from NAND gate.

Derive OR gate from NAND gate

Derive XOR gate from NAND gate.

SystemVerilog

Parameters passing, defparam & localparam

Digital design Interview questions. FPGA Interview. FPGA flow. Guide to Graduate studies in US Pipeline vs. Parallel processing.

2 variable K– map plot is mapped in table below.

Resources

Clock Domain Crossing Discussion with rtl & testbench example.

Ratechange (asynchronous) FIFO design and fifo depth calculation.

Half-adder , Full-adder , 4-bit binary adder , adder-subtractor circuit, overflow with rtl & testbench. Binary Multiplier, Parity error TT

Arithmetic, logical, shift micro-operations . Stack organization, LIFO, RPN discussion. RTL coding guidelines. ICG cell, Assertions, $assertkill, levels.

Clock Domain Crossing Discussion with rtl & testbench example.

Ratechange (asynchronous) FIFO design and fifo depth calculation.

Half-