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Logic micro -operations:

In Logic operations, individual bits of registers are operated with other corresponding register bits.

Example logic operation.

Register A is 4 bits long = 0110

Register B is also 4 bits long with contents 1100.

In Logic operations, individual bits of registers are operated with other corresponding register bits.

Example logic operation.

Register A is 4 bits long = 0110

Register B is also 4 bits long with contents 1100.

Following is the list of logic microoperations that can be performed on the any two registers. Lets assume registers A and B for discussion.

Bit 3

Bit 2

Bit 1

Bit 0

A

0

1

1

0

B

1

1

0

0

A AND B

0

1

0

0

Name

function

AND

F0 = A*B

Bitwise AND. ref

NAND

F1 = (A* B)’

Bitwise NAND

OR

F2=A+B

Bitwise OR ref

NOR

F3=(A+B)’

Bitwise NOR ref

Complement A

F4=A’

Complement each bit of register A.

Complement B

F5=B’

Complement each bit of register B.

XOR

F6=AB’+ A’B

Bitwise XOR. ref

XNOR

F7=(AB’+ A’B)’

Bitwise XNOR ref

Transfer A

F8=A

Unchanged contents of register A

Transfer B

F9=B

Unchanged contents of register B.

Set

F10=1

Set all bits

Clear

F11=0

Clear all bits

A AND (Comp B)

F12=A*B’

(Comp A) AND B

F13=A’*B

A OR (Comp B)

F14=A+B’

(Comp A) OR B

F15=A’+B

Logic operation A AND B is shown in table below

Resources

Digital design resources

Clock Crossing rtl & testbench.

Rate change (asynchronous) FIFO design and fifo depth calculation.

Half-adder , Full-adder , 4-bit binary adder , adder-subtractor circuit, overflow with rtl & testbench. Binary Multiplier, Parity error TT, Arithmetic, logical, shift micro-operations . Stackorganization, LIFO, RPN discussion.

RTL coding guidelines. ICG cell, Assertions, $assertkill, levels.

Digital design Interview questions.

FPGA Interview. FPGA flow. Graduate studies

Pipeline vs. Parallel processing.

Digital design resources

Clock Crossing rtl & testbench.

Rate change (asynchronous) FIFO design and fifo depth calculation.

Half-

Digital design Interview questions.

FPGA Interview. FPGA flow. Graduate studies

Pipeline vs. Parallel processing.

Interview Questions. Main, FPGA, Digital Fundamentals