Home.Verilog.Digital Design.Digital Basics.Python.RF Basics.
Previous.
Next.
Custom Search

Legal Disclaimer

Chip Designing for ASIC/ FPGA Design engineers and Students
FULLCHIPDESIGN
Digital-logic Design...  Dream for many students… start learning front-end…

Legal Disclaimer

@TYH :- 4G LTE Long Term Evolution Tutorial, CloudComputing
PICS
Verilog Tutorial.
Get Noticed:- Submit your own content to be published on fullchipdesign.com

Send it to fullchip@gmail.com

Digital Basics Tutorial.

Logical Shift Left micro-operation RTL

Verilog code and test-bench for logical shift left microoperations.
~\Downloads\fc_v\shift_LL.v.html // Test Bench for generating random numbers
module shift_tb ();
reg clk, rst; 
reg[7:0] x_q;
reg[7:0] x_d;
reg[4:0] q_cnt;

integer k, i;
integer out; 
// clock generation
initial 
begin
    clk = 0;
   forever #10 clk = ~clk;
end
// reset release
initial begin 
    rst = 0;
    # 50 rst = 1;
end
// Use positive edge of clock to shift the register value
// Implement logical left shift
always @(posedge clk or
    negedge rst)
begin
    if (!rst)
    begin
        x_q <= 'hed;
        q_cnt <= 0;
        out = $fopen("shift_LL.vec","w");
    end
    else
    begin
        x_q <= x_d;
        q_cnt <= q_cnt + 1;
        $fdisplay(out, "Pass %d Shift value in hex %b", q_cnt, x_q);
    end
end
// shift logic
always @(*)
begin
    x_d = x_q;
    x_d[0] = 0;
    for (i=0; i<8; i=i+1)
    begin
        x_d[i+1] = x_q[i];
    end
end
endmodule
Simulation results for verilog logical shift left micro-operations from here
Home Shift LSR LSR result Log shift L LSL result Cir shift L CSL result Cir Shift R CSR result
LSR result.
LSL result.
Previous         Next
Related topics: Arithmetic, Logical, Shift micro-operations and digital Overflow with Verilog rtl discussion.
LTE - Long Term Evolution topics from here
Cloud Computing ?
thread of cloud computing is active. Learn more from here.
Interview Questions. Main, FPGA, Digital Fundamentals