Custom Search

Chip Designing for ASIC/ FPGA Design engineers and Students

FULLCHIPDESIGN

Digital-logic Design... Dream for many students… start learning front-end…

Get Noticed:- Submit your own content to be published on fullchipdesign.com

Send it to fullchip@gmail.com

Combination of fundamental logic gates:

Gate 5: NAND. Description: This gate is fundamental for any operation where output is complement of product of all binary inputs.

Output = (Input1 * Input2 …….. * Input N)’

Where, outputs and inputs are all in binary values ’1’ or ’0’.

Description: This gate is fundamental of any operation where output is complement of addition of all binary inputs.

Output = (Input1 + Input2 …….. + Input N)’

Where, outputs and inputs are all in binary values ’1’ or ’0’

Description: This gate is fundamental of any operation where output is low only when two binary inputs are different.

Output = (Input1)’*(Input2)’ + (Input1) * (Input2)

Where, outputs and inputs are all in binary values ’1’ or ’0’

Digital Logic Gates: NAND, NOR & XNOR

X (In 1)

Y (In 2)

Z (Out)

0

0

1

0

1

1

1

0

1

1

1

0

X (In 1)

Y (In 2)

Z (Out)

0

0

1

0

1

0

1

0

0

1

1

0

X (Input 1)

Y (Input 2)

Z (Output)

0

0

1

0

1

0

1

0

0

1

1

1

This gate is also know as universal gate. Any logic can be implemented by only using NAND gates.

Drive Inverter from NAND and drive XOR from NAND

Drive Inverter from NAND and drive XOR from NAND

Resources

Verilog RTL code examples for front-end chip design.

Digital Design Topics

Half-adder , full-adder ,

Adder-sub tractor

Stack Organization - LIFO, RPN

Parity Generation and error checking

Binary multiplier circuit.

CMOS introduction

Digital fundamentals -

RTL coding guidelines. ICG cell, Assertions, $assertkill, levels. Chandle

Pipeline vs. Parallel processing.

Verilog RTL code examples for front-

Half-

Adder-

Stack Organization -

Binary multiplier circuit.

CMOS introduction

Digital fundamentals -

RTL coding guidelines. ICG cell, Assertions, $assertkill, levels. Chandle

Pipeline vs. Parallel processing.

Interview Questions. Main, FPGA, Digital Fundamentals

Universal NAND Gate...

Derive AND gate from NAND gate...

Derive OR gate from NAND gate...

Derive XOR gate from NAND gate...

Derive AND gate from NAND gate...

Derive OR gate from NAND gate...

Derive XOR gate from NAND gate...