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Clock Domain Crossing Discussion with rtl & testbench.

Rate change(asynchronous) FIFO design and fifo depth calculation.

Half-

VHDL rtl -

RTL coding guidelines. ICG cell, Assertions, levels.

Digital design Interview questions.

FPGA Interview. FPGA flow.

Guide to Graduate studies in US

Pipeline vs. Parallel processing.

Overflow in Binary Arithmetic. Discussion with examples.

Overflow Introduction and scenarios

In terms of computing, two numbers are loaded into registers before performing any arithmetic operations. For a number between 0 to 15 we can use a register of length 4 bits. When two 4 bit numbers are added and the result is greater than 4 bits then we get an overflow condition..

Overflow can occur in either of the two following scenarios:-

Adding two positive numbers.

Or, Adding two negative numbers in signed arithmetic.

Overflow can occur in either of the two following scenarios:-

Adding two positive numbers.

Or, Adding two negative numbers in signed arithmetic.

Example1 - Add 2 unsigned binary numbers.

Add two binary numbers 10 and 15 with previous carry = 0.

Sol. Load the values in two registers R1 and R2.

So, R1 = 10 (decimal) = 1010 (in binary A3A2A1A0)

& R2 = 15 (decimal) = 1111 (in binary B3B2B1B0)

So from the binary adder implementation.

Refer binary adder example for detailed calculations.

Result = (Carry = 1) (Sum = 1001)

In this case Overflow is true and result includes the overflow bit. We can use a separate flip-flop to store the result of overflow condition.

Sol. Load the values in two registers R1 and R2.

So, R1 = 10 (decimal) = 1010 (in binary A3A2A1A0)

& R2 = 15 (decimal) = 1111 (in binary B3B2B1B0)

So from the binary adder implementation.

Refer binary adder example for detailed calculations.

Result = (Carry = 1) (Sum = 1001)

In this case Overflow is true and result includes the overflow bit. We can use a separate flip-

Example3 - Add 2 signed number to not produce overflow.

Example2 - Add 2 signed number to produce overflow.

Overflow can never occur when adding a positive number to a negative number. The reason being the result is always smaller than the original larger number. We will discuss the overflow condition with examples below:-

Hot Topics @FCD

Cloud Computing

Cloud Computing

Digital Logic fundamentals topics

Digital basics tutorial

Binary number discussion, 1 and 2 complement discussion,

Binary arithmetic, Signed Magnitude, overflow, examples

Gray coding, Binary coded digital (BCD) coding, BCD addition

Digital logic gates basic (AND, OR, XOR, NOT) and derived (NAND, NOR and XNOR). Drive XOR from NAND gates. Drive XOR from NOR gates

Discussion of Boolean Algebra with examples.

Duality Principle, Huntington Postulates, Theorems of Boolean Algebra - discussion with examples,

Boolean Functions,

Canonical and Standard Forms, Minterms and Maxterms

Sum of Minterms, Product of Maxterms or Canonical Forms,

Karnaugh map or K-map discussion 2, 3, ,4 and 5 var’s

Prime Implicant and Gate level minimization examples.

Digital basics tutorial

Binary number discussion, 1 and 2 complement discussion,

Binary arithmetic, Signed Magnitude, overflow, examples

Gray coding, Binary coded digital (BCD) coding, BCD addition

Digital logic gates basic (AND, OR, XOR, NOT) and derived (NAND, NOR and XNOR). Drive XOR from NAND gates. Drive XOR from NOR gates

Discussion of Boolean Algebra with examples.

Duality Principle, Huntington Postulates, Theorems of Boolean Algebra -

Canonical and Standard Forms, Minterms and Maxterms

Sum of Minterms, Product of Maxterms or Canonical Forms,

Karnaugh map or K-

Prime Implicant and Gate level minimization examples.

Interview Questions. Main, FPGA, Digital Fundamentals

Return to Verilog Tutorial

Interview Questions. Main, FPGA, Digital Fundamentals