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Verilog Initial stmts IF-ELSE Case stms Readmemh Function Testbench Binary to Gray Clock Crossing Half-adder Full-adder Tristate buffer Adder tb Counter_enable Blocking Operators Shift LSR Random Nos Sync RAM Verilog Tutorial

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Verilog Tutorial.
Digital Basics Tutorial.

StepDisplay the values from the text file on the compiler screen.

 

// Verilog code example for file operations

// module declaration

module file_readmemh; 

/* Declare a array 4 word deep 20 locations wide for 20/4 = 5 hexadecimal words */ 

reg [19:0] data [0:3];

// initialize the hexadecimal reads from the vectors.txt file

initial $readmemh("vectors.txt", data);

/* declare an integer for the conditional

statement to read values from test file */

integer i;

/*read and display the values from the text file on screen*/ 

initial begin

        $display("rdata:");

        for (i=0; i < 4; i=i+1)

        $display("%d:%h",i,data[i]);

end     

endmodule 

 

Program. File operation using ‘readmemh’ for reading hex values from test files. 

Step. Verilog code example for file operations.

Step.  Declare a array of 4 word deep and 20 locations wide to store 5 hexadecimal values.

Step.  Use readmemh’ command to read hexadecimal values.

Step.  Declare an integer to set a pointer to read values from test file.

Verilog readmemh (or readmemb) function

Results

Input => File vectors.txt =>

12abc  34def  1dead 2bee1

Output =>

0:12abc

1:34def

2:1dead

3:2bee1

 

 

Do you like Brain teasers? Q. Simplify Boolean Functions F = xyz + x’y + xyz’.
Answer: click here Digital Logic fundamentals
Readmemb is similar to readmemh with only difference of binary interpretation of the text file. Required format of input text file is binary.   
Interview Questions. Main, FPGA, Digital Fundamentals
LTE - Long Term Evolution topics from here
PICS

SystemVerilog

Parameters passing, defparam & localparam

Alias, Array, Assertions