Home.Verilog.Digital Design.Digital Basics.Python.RF Basics.
Custom Search

Legal Disclaimer

Chip Designing for ASIC/ FPGA Design engineers and Students
Digital-logic Design...  Dream for many students… start learning front-end…

Legal Disclaimer

@TYH :- 4G LTE Long Term Evolution Tutorial, CloudComputing
Verilog Tutorial.
Get Noticed:- Submit your own content to be published on fullchipdesign.com

Send it to fullchip@gmail.com

Digital Basics Tutorial.

Minimum Detectable Signal (MDS)

MDS is a level 3 dB above the noise floor. The value of MDS is calculated with the help of following formula.


k = Boltzmann’s constant

T = Temperature in degree Kelvin

B = Noise Bandwidth

F = Noise Factor

Dynamic Range (DR)

Range of input powers at which a receiver can operate is called dynamic range of the system

Lower End: - Lowest detectable input power is sometimes characterized by the MDS (Minimum Detectable Signal)

Upper End: - Third order intermodulation products (IP3) limits the performance of the receiver at the upper end

A commonly accepted equation/definition for dynamic range is:

Signal to Noise Ratio (SNR).

Noise Factor (F).  Cascaded system F.

Noise Figure (NF).

Minimum Detectable Signal (MDS).

Intermodulation (IM) distortion.

Second order intermodulation products.

Third order intermodulation products.

IP3 (Third Order Intercept) point.

Dynamic Range (DR)



Spurious outputs

Gain control


Dynamic Range = 2/3(IP3 - MDS)
MDS & DR IM distortion IP3 IP3 Plot RX characterization Antenna Sel Cascade F PLL