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Intermodulation (IM) distortion

Intermodulation distortion is a scenario where signals from outside the monitored
channel combine nonlinearly to produce frequencies within monitored channel frequency
range. This intermodulation distortion is a completely undesirable but un-

Distortions in a system are represented with the help of Taylor series. Each term in Taylor series is represented as in formula below.

Where ft1 and ft2 are the frequencies of two different inputs signals to the system. Variable n can have any integer value.

Solving the above equation for n=2 will results in terms with frequency.

M is a variable which takes the values 0,1 and 2

So we get, m = 0,

Second order distortion product =

m = 1,

Second order distortion product =

m = 2,

Second order distortion product =

Lets discuss following Intermodulation products:-

Second Order Intermodulation products are discussed below.

Access Third order Intermodulation products from here..

Second Order Intermodulation products are discussed below.

Access Third order Intermodulation products from here..

Resources

Digital design resources

Clock Domain Crossing Discussion with

rtl & testbench example.

Rate change(asynchronous) FIFO design and fifo depth calculation.

Half-adder , Full-adder , 4-bit binary adder , adder-subtractor circuit, overflow with rtl & testbench. Binary Multiplier, Parity error TT

Arithmetic, logical, shift micro-operations . Stack organization, LIFO, RPN discussion.

VHDL rtl - Synchronous flip-flop , latch, shim to improve timing and counter example

RTL coding guidelines. ICG cell, Assertions, $assertkill, levels.

Digital design Interview questions.

FPGA Interview. FPGA flow.

Guide to Graduate studies in US

Pipeline vs. Parallel processing.

Digital design resources

Clock Domain Crossing Discussion with

rtl & testbench example.

Rate change(asynchronous) FIFO design and fifo depth calculation.

Half-

VHDL rtl -

Digital design Interview questions.

FPGA Interview. FPGA flow.

Guide to Graduate studies in US

Pipeline vs. Parallel processing.

LTE - Long Term Evolution topics from here

Return to Verilog Tutorial

Interview Questions. Main, FPGA, Digital Fundamentals

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