Chip Designing for ASIC/ FPGA Design engineers and Students
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Setup, Hold time & metastability of flop
Setup time - Setup time is measured at the input of the flip-flop with respect to rising/falling edge of the clock to the flop. The time signifies the minimum duration of data stability before the arrival of rising/falling clock edge. With this requirement the flops will reliably sample the data at the output.
Hold time - Hold time is measured at the output of the flip-flop with respect to rising/falling edge of the clock to the flop. The time signifies the minimum duration of data stability at the output after the rising/falling clock edge. With this requirement the output flip-flop data is stable enough to drive the digital logic.
Metastability - It’s a condition on the output signal of a flip-flop due setup or hold time violations discussed before.
A metastable signal does not represent a high ’1’ or a low ’0’ and results in unstable output or a glitch to the digital circuit.
Rate change(asynchronous) FIFO design and fifo depth calculation.
Half-adder, Full-adder, 4-bit binary adder , adder-subtractor circuit, overflow with rtl & testbench. Binary Multiplier, Parity error TT
Arithmetic, logical, shift micro-operations. Stack organization, LIFO, RPN discussion.
VHDL rtl - Synchronous flip-flop, latch, shim to improve timing and counter example
RTL coding guidelines. ICG cell, Assertions, $assertkill, levels.
Digital design Interview questions.
FPGA Interview. FPGA flow.
Guide to Graduate studies in US
Pipeline vs. Parallel processing.