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Verilog Tutorial.
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Digital Basics Tutorial.
Setup, Hold time & metastability of flop
Setup time - Setup time is measured at the input of the flip-flop with respect to rising/falling edge of the clock to the flop.  The time signifies the minimum duration of data stability before the arrival of rising/falling clock edge. With this requirement the flops will reliably sample the data at the output.
Hold time - Hold time is measured at the output of the flip-flop with respect to rising/falling edge of the clock to the flop.  The time signifies the minimum duration of data stability at the output after the rising/falling clock edge. With this requirement the output flip-flop data is stable enough to drive the digital logic.
Clock Crossing.
Async FIFO.
Half Adder.
Full Adder.
Binary Adder.
Overflow.
Overflow Det.
Adder-Subtractor.
Multiplier.
Parity check.
RTL guidelines.
NAND to INVERTER.
VHDL.
RTL.
Arith Micro-ops.
Stack Org.
Parallel proc..
Pipeline proc.
CMOS Intro.
Metastability - It’s a condition on the output signal of a flip-flop due setup or hold time violations discussed before.

A metastable signal does not represent a high ’1’ or a low ’0’ and results in unstable output or a glitch to the digital circuit.    
Interview Questions. Main, FPGA, Digital Fundamentals
LTE - Long Term Evolution topics from here