Home.Verilog.Digital Design.Digital Basics.Python.RF Basics.
Previous.Next.
Custom Search

Legal Disclaimer

Chip Designing for ASIC/ FPGA Design engineers and Students
FULLCHIPDESIGN
Digital-logic Design...  Dream for many students… start learning front-end…

Legal Disclaimer

@TYH :- 4G LTE Long Term Evolution Tutorial, CloudComputing
PICS
Verilog Tutorial.
Get Noticed:- Submit your own content to be published on fullchipdesign.com

Send it to fullchip@gmail.com

Digital Basics Tutorial.

Example:- Signed Magnitude Arithmetic

Final Answer. The arithmetic sum of two numbers +25 and -37 using signed magnitude method is -12 (10001100)  

Store Sign as MSB Bit = 1

Example 1: Add -37 to +25 using 2’s complement & signed magnitude

2’s complement of remaining bits as result = 0001100

Binary Numbers 1s_complement 2s_complement Binary Subtraction Binary Sub. Ex's Sign_magnitude SignM EX Gray Coding BCD coding Digital gates NAND NOR & XNOR Theorems Boolean Functions BFunc Examples Minterm Maxterm Sum of Minterms Prdt of Maxterms 2 var K-map 3 var K-map 4 var K-map 5 var K-map Prime Implicant PI example K-map Ex's KMap minimization 2 var EX
+25
In signed convention
00011001
-37
In 2’s complement
11011011
Equivalent result
11110100
Interview Questions. Main, FPGA, Digital Fundamentals
LTE - Long Term Evolution topics from here