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Verilog Tutorial.
Digital Basics Tutorial.
Verilog - RTL (Register Transfer Level) examples
Verilog is a programming language designed to code hardware at register transfer level. The digital hardware consists of concurrent and sequential events. A synchronous digital circuit is modeled with following considerations:
<> A circuit consists of sequential & parallel events.
<> Interim results are stored in registers.
<> Registers are generally implemented as D Flip Flops.
<> Data is transferred between registers which are synchronous to each other.
Verilog Tutorial is covered online here.
Verilog operators - Building blocks of Verilog. Follow topics in verilog tutorial to learn the language.  

Verilog Initial Statements -  Used in Test benches for generating stimulus (clocks, resets, etc).

Conditional Statements - ‘IF-ELSE’ statement and use in ‘always’ block. ‘case’ statement

Synchronous Counters. Implementation example.

Complete Verilog ‘readmemh’ code to read hex values in a test-bench.

Functions and its call in verilog tutorial.

Verilog file read write operations.
Verilog testbench example. More examples are presented online under Verilog tutorial.

Verilog Binary to Gray Code conversion example.

Verilog code for clock domain crossing.
Half-adder, Full-adder, Tri-state buffer implementation in verilog. Testbench to validate half-adder, full-adder and tri-state buffer.
Readmemb click here
Shift micro operations - Logical Shift Right (LSR) verilog code and simulation results. LSR discussion here. Logical Shift left (LSL)
verilog code and simulation results. LSL discussion here. Circular Shift Right (CSR) verilog code, results, discussion. Circular Shift Right (CSR) verilog code, simulation results and discussion.

Random number generation in test-bench and use of $fdisplay.

Memory - synchronous RAM implementation and test-bench
Initial stmts IF-ELSE Case stms Readmemh Function Testbench Binary to Gray Clock Crossing Half-adder Full-adder Tristate buffer Adder tb Counter_enable Blocking Operators Shift LSR Random Nos Sync RAM Verilog Tutorial
LTE - Long Term Evolution topics from here
Interview Questions. Main, FPGA, Digital Fundamentals
Return to Verilog Tutorial