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Following block diagram can used to implement clock domain crossing for phase offset
Link to verilog rtl for clock domain crossing.
Check below the block diagram for clock domain crossing
Clock domain crossing discussion
Verilog code for clock domain crossing from link embedded.
Double clocking through flops is generally implemented to avoid the metastability
arising from setup or hold time violations.
Access setup and hold time details from here.
Metastability is a condition on the output signal of a flip-flop due setup or hold
time violation on the digital input signal.
A metastable signal does not represent a high ’1’ or a low ’0’ and results in unstable
output or a glitch to the digital circuit.