Home Verilog Digital Design Digital Basics Python RF Basics

Legal Disclaimer

Chip Designing for ASIC/ FPGA Design engineers and Students
FULLCHIPDESIGN
Digital-logic Design...  Dream for many students… start learning front-end…
Topics @TYH :- 4G LTE Tutorial, GVIM editor, Smart-Phone, Cloud Computing
FCD
Custom Search

Feedback ? Send it to admin@fullchipdesign.com or join me at fullchip@gmail.com

Legal Disclaimer

Previous.
Next.
Introduction Operators Initial stms Block vs. Non Blk IF-ELSE, CASE FORLOOP File Operations Read .bin format Function Call Testbench Random Numbers Shift Micro-ops Sync RAM Mem Generate Assertions Signed RTL
Verilog Tutorial.
Digital Basics Tutorial.
As long as an assertion holds true no messages are populated in the logic simulation’s. Whenever assertions fails, simulator produces ‘Error messages’.

Types of Assertions:-
1) Immediate assertion. 2) Concurrent assertions.

The two type of assertions are discussed in details with examples below.
Immediate Assertions -

Immediate assertions are executed only once and are mostly implemented within ‘initial blocks’. Due to limited use cases its not widely used and limited to simulations.

Example of immediate assertion below:-

assert (A==B) $display(“Pass”);
   else $error(“Fail, reporting Error”);

Failure of assertion is reported by else statement. In ‘else’ branch we can also include severity of the failure. The level of severity varies from $info, $warning, $error or $fatal. The $error is the default severity in SystemVerilog.
Concurrent Assertions -

The concurrent assertions are tied closely to the RTL design to behave inline with the implementation logic. These assertions are most valuable and widely used. Its useful for both formal verification and behavioral simulations.

There are two types of concurrent assertions :-

Assertions checking the property only with rising edges of the clock.
Assertions which are always active in time and properties are constantly validated.
Example of concurrent assertions:-

assert property (@posedge clk) (fifo_full && fifo_wr);

Checks that the FIFO full flag and FIFO write data control is never set high (or 1) at any rising edge of the clock.
Interview Questions. Main, FPGA, Digital Fundamentals
Assertions in Digital Logic Design - RTL (Verilog, SystemVerilog etc.)
An assertion is a logical state defined to monitor the occurrence of certain events in the logic design during behavioural simulations. Defining logical states for assertions are implemented as properties (or rules). Each property can be visualized as a Boolean Expression.
Evolved Packet Core (EPC) system architecture for all IP.Mobility Management Entity (MME),
Serving System (S) Architecture (A) Evolution (E) Gateway or Serving Gateway SGW.
Packet Data Network (PDN) SAE Gateway
Enhanced Packet Data Gateway (ePDG)
Multiple antenna techniques - MIMO, Adaptive antenna systems - AAS and Antenna diversity - AD
Return to Verilog Tutorial
Interview Questions. Main, FPGA, Digital Fundamentals
Mem Generate.
Signed RTL.