Custom Search

Chip Designing for ASIC/ FPGA Design engineers and Students

FULLCHIPDESIGN

Digital-logic Design... Dream for many students… start learning front-end…

Get Noticed:- Submit your own content to be published on fullchipdesign.com

Send it to fullchip@gmail.com

Verilog Testbench for Bitwise operations - Negation, AND, OR and XOR.

Bitwise - Bitwise operations are performed on individual bits of registers. In our example we use registers (r1 and r2). Results are stored in register ‘acc’.

(

);

$monitor (" Time = %t, ACC = %b", $time, acc);

r1 = 2'b10;

r2 = 2'b11;

/* Negation */

acc = ~r1;

/* Bitwise OR */

# 5 acc = r1 | r2;

#15

r1 = 2'b00;

r2 = 2'b01;

/* Bitwise AND */

# 5 acc = r1 & r2;

/* Bitwise XOR */

# 5 acc = r1 ^ r2;

$finish;

C:\iverilog\samples>..\bin\vvp step

Negation

Time = 0, ACC = 01

Bitwise OR

Time = 5, ACC = 11

Bitwise AND

Time = 25, ACC = 00

Bitwise XOR

Time = 30, ACC = 01

Negation

Time = 0, ACC = 01

Bitwise OR

Time = 5, ACC = 11

Bitwise AND

Time = 25, ACC = 00

Bitwise XOR

Time = 30, ACC = 01

Simulation Results for the above code are shown below:

Top Tech Topics @FCD

K-map - 2,3,4,5 var & Prime Implicant discussion

Verilog - learn with examples

Interview questions and hints

Arithmetic, logical, shift micro-operations , Overflow

Interview Questions. Main, FPGA, Digital Fundamentals

K-

Verilog -

Interview questions and hints

Arithmetic, logical, shift micro-

Interview Questions. Main, FPGA, Digital Fundamentals

Digital Logic fundamentals topics @ fcd

Binary number discussion, 1 and 2 complement discussion,

Binary arithmetic, Signed Magnitude, overflow, examples

Gray coding, Binary coded digital (BCD) coding, BCD addition

Digital logic gates basic (AND, OR, XOR, NOT) and derived (NAND, NOR and XNOR). Drive XOR from NAND gates. Drive XOR from NOR gates

Discussion of Boolean Algebra with examples.

Duality Principle, Huntington Postulates, Theorems of Boolean Algebra - discussion with examples, Boolean Functions, Canonical and Standard Forms, Minterms and Maxterms

Sum of Minterms, Product of Maxterms or Canonical Forms,

Karnaugh map or K-map discussion 2, 3, ,4 and 5 var’s

Prime Implicant and Gate level minimization examples.

Binary number discussion, 1 and 2 complement discussion,

Binary arithmetic, Signed Magnitude, overflow, examples

Gray coding, Binary coded digital (BCD) coding, BCD addition

Digital logic gates basic (AND, OR, XOR, NOT) and derived (NAND, NOR and XNOR). Drive XOR from NAND gates. Drive XOR from NOR gates

Discussion of Boolean Algebra with examples.

Duality Principle, Huntington Postulates, Theorems of Boolean Algebra -

Karnaugh map or K-

Prime Implicant and Gate level minimization examples.

Interview Questions. Main, FPGA, Digital Fundamentals

Solved Examples for 3 variable Kmaps

1. F(x,y,z) = (0,1,6,7) - Minimization, on this page.

2. F(x,y,z) = (0,1,4,5,6,7) - Minimization from here.

3. F(x,y,z) = (3,4,6,7) - Minimization from here.

4. F(x,y,z) = (0,1,2,3,4,5,6,7) - Minimization from here.

1. F(x,y,z) = (0,1,6,7) -

LTE - Long Term Evolution topics from here

5 Steps required to build a functional FPGA load (valid for most EDA flows)

How to implement a Integrated Clock Gating (ICG) cell from vendor library.

CMOS Digital Integrated Circuit design for VLSI.