﻿ Verilog Bitwise operators and, or, not, xor, \$time, \$monitor and initial statements.
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Verilog Testbench for Bitwise operations - Negation, AND, OR and XOR.
Bitwise - Bitwise operations are performed on individual bits of registers. In our example we use registers (r1 and r2). Results are stored in register ‘acc’.
C:\iverilog\samples\verilog_operators.v.html module tb_opereators
(
);

reg[1:0] r1;
reg[1:0] r2;
reg[1:0] acc;

initial begin
\$monitor (" Time = %t, ACC = %b", \$time, acc);
r1 = 2'b10;
r2 = 2'b11;
/* Negation */
acc = ~r1;
/* Bitwise OR */
# 5 acc = r1 | r2;
#15
r1 = 2'b00;
r2 = 2'b01;
/* Bitwise AND */
# 5 acc = r1 & r2;
/* Bitwise XOR */
# 5 acc = r1 ^ r2;
\$finish;

end

endmodule
C:\iverilog\samples>..\bin\vvp step

Negation
Time =                    0, ACC = 01

Bitwise OR
Time =                    5, ACC = 11

Bitwise AND
Time =                   25, ACC = 00

Bitwise XOR
Time =                   30, ACC = 01
Simulation Results for the above code are shown below:
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