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Free running verilog counters code with asynchronous reset and synchronous reset.

Second implementation, counter B will get reset to zero with positive edge of reset and will stay there till reset is cleared. After reset is cleared (or 0) the counter will act as free running counter with positive edge of clock. So as long clock is running and reset is 0,  counter will be incrementing till 2^8-1 (=127) value and then restart from 0.  

Verilog RTL code examples for counter are discussed below. In this code we have implemented three free running counters with different reset scenarios.

 

First implementation, counter A is free running counter with positive edge of clock. So as long clock is running counter will be incrementing till 2^8-1 (=127) value and then restart from 0.

 

 

Interview Questions. Main, FPGA, Digital Fundamentals
~\Documents\fullchipdesign\verilog_code\frun_cnt.v.html
    module frun_counters (clock, reset, mon_counter_a, mon_counter_b, mon_counter_c);
    input   clock;
    input   reset;
    output  [7:0]  monitor_counter_a, monitor_counter_b, monitor_counter_c;
    
    reg [7:0] cnt_A, cnt_B, cnt_C;
    
    // synchronous free run counter
    always @(posedge clock) cnt_A <= cnt_A + 1;
    
    // synchronous free run counter with synchronous reset
    always @(posedge clock or posedge reset)
      if (reset) cnt_B <= 0;
      else cnt_B <= cnt_B + 1;
    
    // synchronous free run counter with asynchronous reset
    always @(posedge clock or negedge reset)
      if (~reset) cnt_C <= 0;
      else cnt_C <= cnt_C + 1;
    
    /* map the counter values to outputs to be monitored
       outside the block. */
    assign monitor_counter_a = cnt_A;
    assign monitor_counter_b = cnt_B;
    assign monitor_counter_c = cnt_C;
    
    endmodule
    
    

Third implementation, counter C will get reset to zero with negative edge of reset and will stay there till reset is set. After reset is set (or 1) the counter will act as free running counter with positive edge of clock. So as long clock is running and reset is 1,  counter will be incrementing till 2^8-1 (=127) value and then restart from 0.  

Verilog rtl code for above three counter are discussed below.

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Interview Questions. Main, FPGA, Digital Fundamentals