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/*Function declaration and calling a function is discussed in this section.*/

reg [5:0] counter_binary, counter_binary_reg, counter_gray, counter_gray_reg;

integer count, file_wr;

/*Function to get Gray code from Binary code*/

function[5:0] binary2gray ;

input[5:0] value;

integer i;

begin

binary2gray[5] = value[5];

for (i=5; i>0; i = i - 1)

binary2gray[i-1] = value[i] ^ value[i - 1];

end

endfunction

//Calling a function

always @(*)

begin

counter_binary = counter_binary_reg;

counter_gray = binary2gray(counter_binary_reg);

end

endmodule

reg [5:0] counter_binary, counter_binary_reg, counter_gray, counter_gray_reg;

integer count, file_wr;

/*Function to get Gray code from Binary code*/

function[5:0] binary2gray ;

input[5:0] value;

integer i;

begin

binary2gray[5] = value[5];

for (i=5; i>0; i = i -

endfunction

//Calling a function

always @(*)

begin

counter_binary = counter_binary_reg;

counter_gray = binary2gray(counter_binary_reg);

end

endmodule

Verilog Function declaration and call.

Resources

Verilog RTL code examples for front-end chip design.

Digital Design Topics

Half-adder , full-adder ,

Adder-sub tractor

Stack Organization - LIFO, RPN

Parity Generation and error checking

Binary multiplier circuit.

CMOS introduction

Digital fundamentals -

RTL coding guidelines. ICG cell, Assertions, $assertkill, levels. Chandle

Pipeline vs. Parallel processing.

Verilog RTL code examples for front-

Half-

Adder-

Stack Organization -

Binary multiplier circuit.

CMOS introduction

Digital fundamentals -

RTL coding guidelines. ICG cell, Assertions, $assertkill, levels. Chandle

Pipeline vs. Parallel processing.

Arithmetic, logical and shift microoperations.

Binary to Gray code conversion

Readmemh, Readmemb. Random numbers

Memory Implementation - sync Ram and

Binary to Gray code conversion

Readmemh, Readmemb. Random numbers

Memory Implementation -

Complete usage of the above verilog function declaration and call is discussed in program at following link.

Digital Logic fundamentals topics @ fcd

Digital basics tutorial

Binary number discussion, 1 and 2 complement discussion,

Binary arithmetic, Signed Magnitude, overflow, examples

Gray coding, Binary coded digital (BCD) coding, BCD addition

Digital logic gates basic (AND, OR, XOR, NOT) and derived (NAND, NOR and XNOR).

Drive XOR from NAND gates. Drive XOR from NOR gates

Discussion of Boolean Algebra with examples.

Duality Principle, Huntington Postulates, Theorems of Boolean Algebra - discussion with examples, Boolean Functions, Canonical and Standard Forms, Minterms & Maxterms, Sum of Minterms, Product of Maxterms or Canonical Forms,

Karnaugh map or K-map discussion 2, 3, ,4 and 5 var’s. Prime Implicant and Gate level minimization examples.

Digital basics tutorial

Binary number discussion, 1 and 2 complement discussion,

Binary arithmetic, Signed Magnitude, overflow, examples

Gray coding, Binary coded digital (BCD) coding, BCD addition

Digital logic gates basic (AND, OR, XOR, NOT) and derived (NAND, NOR and XNOR).

Drive XOR from NAND gates. Drive XOR from NOR gates

Discussion of Boolean Algebra with examples.

Duality Principle, Huntington Postulates, Theorems of Boolean Algebra -

Interview Questions. Main, FPGA, Digital basics

Resources

Digital design resources

Clock Crossing rtl & testbench. Rate change FIFO design and fifo depth calc. Half-adder , Full-adder , 4-bit binary adder , adder-subtractor circuit, overflow with rtl & testbench. Binary Multiplier, Parity error TT, Arithmetic, logical, shift micro-operations . Stack organization, LIFO, RPN discussion.

ICG cell, Assertions, $assertkill, levels. Digital design Interview questions. FPGA Interview. FPGA flow.

Guide to Graduate studies in US Pipeline vs. Parallel processing.

Digital design resources

Clock Crossing rtl & testbench. Rate change FIFO design and fifo depth calc. Half-

Guide to Graduate studies in US Pipeline vs. Parallel processing.

Interview Questions. Main, FPGA, Digital basics.

Introduction to Verilog RTL

Verilog Operators.

Initial Statements in verilog.

Clock and Reset generation.

Blocking vs. Non-blocking Statements.

Conditional Statements & ‘always’ block.

Counter Implementation. File Operations - $fopen, $fclose, $fdisplay, $fscanf

Read binary or hex format files - $readmemh, $readmemb. FOR Loop use in verilog code

Verilog Operators.

Initial Statements in verilog.

Clock and Reset generation.

Blocking vs. Non-

Conditional Statements & ‘always’ block.

Counter Implementation. File Operations -

Read binary or hex format files -

A function is discussed below to convert binary number to gray code number. The name of function is quite descriptive and we will be using this function later in complete programs. Declaration of verilog functions are always associated with function calls.

LTE - Long Term Evolution topics from here

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