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Introduction Operators Initial stms Block vs. Non Blk IF-ELSE, CASE FORLOOP File Operations Read .bin format Function Call Testbench Random Numbers Shift Micro-ops Sync RAM Mem Generate Assertions Signed RTL
Verilog Tutorial.
Digital Basics Tutorial.
Verilog RTL code to implement synchronous RAM (Random Access Memory) and also provide a test-bench to validate it is discussed on previous pages.
Verilog Generate
Generate is used in Verilog to instantiate multiple instances of Memory block without manually declaring it.
Code snippet to generate multiple instances of Memory is discussed on this page.
~\Desktop\FCD\fv.v.html // Test Bench for memory modeling
module memory_tb ();
reg clk, rst; 

reg      read_rq;
reg      write_rq;
reg[5:0] rw_address;
reg[31:0] write_data;
wire[31:0] read_data;
reg [6:0] q_cnt;

integer seed;
integer out, rout;

initial 
begin
    clk = 0;
   forever #10 clk = ~clk;
end

initial begin 
    rst = 0;
    # 50 rst = 1;
end

always @(posedge clk or
    negedge rst)
begin
    if (!rst)
    begin 
     q_cnt <= 0;
     write_data <= 'b0;
     out = $fopen("mem_ram.vec","w");
     rout = $fopen("mem_ram_read.vec","w");
    end
    else
    begin
        if (q_cnt < 65)
        begin
            q_cnt <= q_cnt+1;
            write_data <= $random(seed) & 'hFFFF;
            read_rq <= 0;
            write_rq <= 1;
            rw_address <= q_cnt;
            #10 $fdisplay(out, "Address::%d:: %b :: -- contents in hex %h", rw_address, write_data, write_data);
        end
        else
        begin
            q_cnt <= q_cnt;
            write_data <= write_data;
            rw_address <= $random(seed) & 'h3F;
            read_rq <= 1;
            write_rq <= 0;
            #10 $fdisplay(rout,"Address::%d:: %b :: -- read contents in hex %h", rw_address, read_data, read_data);
        end
    end
end


mem_ram_sync u_dut_ram (
    .clk(clk),
    .rst(rst),
    .read_rq(read_rq),
    .write_rq(write_rq),
    .rw_address(rw_address),
    .write_data(write_data),
    .read_data(read_data)
);

genvar i;

generate
    for (i=0; i <4; i=i+1)
    begin
        :MEM mem_ram_sync M (clk,
                        rst,
                        read_rq,
                        write_rq,
                        rw_address,
                        write_data[(i*8+7):i*8],
                        read_data[(i*8+7):i*8]
                       );
    end
endgenerate


endmodule

Sync RAM.
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