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Introduction Operators Initial stms Block vs. Non Blk IF-ELSE, CASE FORLOOP File Operations Read .bin format Function Call Testbench Random Numbers Shift Micro-ops Sync RAM Mem Generate Assertions Signed RTL
Verilog Tutorial.
Digital Basics Tutorial.

Register transfer level (RTL) is used to create a high level description of a synchronous digital circuit. In this coding language the hardware priority is encoded using if-else and case stms.

Conditional If  - Else statements: Its used to generate priority logic in RTL. This construct can be used to code both synchronous and combinational logic.

Synchronous priority logic generation: In this scenario entire logic within always block is executed in parallel with respect to a reference clock edge. Operator, ‘<=’ is used as non-blocking operator.

 

Combinational logic generation :-

 

In this scenario the logic is implemented independent to clock edge. All statements in a always block are executed in sequence. Operator, ‘=‘ is used as blocking operator in Verilog RTL

Verilog Code snippet below. Access complete code from testbench example.

 

reg r_packet_in;

reg packet_in;

always@(posedge clk_1fs or negedge rst_n)

begin

    if (!rst_n) begin

        r_packet_in <= 'b0;

    end

    else begin

        r_packet_in <= packet_in;

    end

End

 

Check the complete implementation of the above logic in verilog testbench example.

Verilog Conditional statements and Counter code.

Verilog Conditional Case Statements & counter code.

Case statements are used in RTL design to model states in Finite State Machine and for generating conditional statements based on value of a particular register. Case statement implementation is shown below.

Synchronous Counter Example

// Always block to Implement counters

always@(posedge clk_1fs or negedge rst_n)

begin

    if (!rst_n) begin

        r_packet_in <= 'b0;

        r_count <= 'b0;

        r_rd_count <= 'b0;

        r_wr_en <= 'b0;

        r_rd_en <= 'b0;

    end

    else begin

        r_packet_in <= packet_in;

        r_count <= count + 1 ;

        r_rd_count <= rd_count + 1 ;

        r_wr_en <= wr_en;

        r_rd_en <= rd_en;

 end end

 

Counters are extensively used in synchronous RTL. In current implementation, its used for keeping track of packets. Check the complete usage of the counter code in the test bench example.  
Check the counter code in the test bench example.  
Block vs. Non Blk.
FORLOOP.
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case (r_count)  

    10 : begin 

           packet_in = 'haa;

           wr_en = 'b1;

         end 

    11 : begin 

           packet_in = 'hbb;

           wr_en = 'b1;

         end

    12 : begin 

          packet_in = 'hcc;

          wr_en = 'b1;

        end

    13 : begin                  

          packet_in = 'hdd;

        wr_en= 'b1;            

        end                        

endcase 

 

 

Interview Questions. Main, FPGA, Digital Fundamentals
Solved 3 var K-map Examples
1. F(x,y,z) =sum(0,1,6,7) - Minimization.
2. F(x,y,z) =sum(0,1,4,5,6,7) - Minimization.
3. F(x,y,z) =sum(3,4,6,7) - Minimization.
4. F(x,y,z) =sum(0,1,2,3,4,5,6,7) - Minimization.
Four variable K-Map minimization example.
1. F(x,y,w, z) = (0,1,2,3,4,6,11,14)
2. F(x,y,w, z) = (0,2,4,6,12,14)
3. F(x,y,w, z) = (0,2,5,7,8,11,13,15)

Gate level minimization of above example is explained in next section. Click here