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Register transfer level (RTL) is used to create a high level description of a synchronous
digital circuit. In this coding language the hardware priority is encoded using if-

Conditional If -

Synchronous priority logic generation: In this scenario entire logic within always
block is executed in parallel with respect to a reference clock edge. Operator, ‘<=’
is used as non-

Combinational logic generation :-

In this scenario the logic is implemented independent to clock edge. All statements in a always block are executed in sequence. Operator, ‘=‘ is used as blocking operator in Verilog RTL

Verilog Code snippet below. Access complete code from testbench example.

reg r_packet_in;

reg packet_in;

always@(posedge clk_1fs or negedge rst_n)

begin

if (!rst_n) begin

r_packet_in <= 'b0;

end

else begin

r_packet_in <= packet_in;

end

End

Check the complete implementation of the above logic in verilog testbench example.

Verilog Conditional statements and Counter code.

Verilog Conditional Case Statements & counter code.

Case statements are used in RTL design to model states in Finite State Machine and for generating conditional statements based on value of a particular register. Case statement implementation is shown below.

// Always block to Implement counters

always@(posedge clk_1fs or negedge rst_n)

begin

if (!rst_n) begin

r_packet_in <= 'b0;

r_count <= 'b0;

r_rd_count <= 'b0;

r_wr_en <= 'b0;

r_rd_en <= 'b0;

end

else begin

r_packet_in <= packet_in;

r_count <= count + 1 ;

r_rd_count <= rd_count + 1 ;

r_wr_en <= wr_en;

r_rd_en <= rd_en;

end end

Counters are extensively used in synchronous RTL. In current implementation, its used for keeping track of packets. Check the complete usage of the counter code in the test bench example.

Digital design resources

Clock Domain Crossing Discussion with

rtl & testbench example.

Rate change (asynchronous) FIFO design and fifo depth calculation.

Half-adder , Full-adder , 4-bit binary adder , adder-subtractor circuit, overflow with rtl & testbench. Binary Multiplier, Parity error TT

Arithmetic, logical, shift micro-operations . Stack organization, LIFO, RPN discussion.

VHDL rtl - Synchronous flip-flop , latch, shim to improve timing and counter example

RTL coding guidelines. ICG cell, Assertions, $assertkill, levels.

Digital design Interview questions.

FPGA Interview. FPGA flow.

Guide to Graduate studies in US

Pipeline vs. Parallel processing.

Clock Domain Crossing Discussion with

rtl & testbench example.

Rate change (asynchronous) FIFO design and fifo depth calculation.

Half-

VHDL rtl -

RTL coding guidelines. ICG cell, Assertions, $assertkill, levels.

Digital design Interview questions.

FPGA Interview. FPGA flow.

Guide to Graduate studies in US

Pipeline vs. Parallel processing.

Digital Logic fundamentals topics @ fcd

Digital basics tutorial

Binary number discussion, 1 and 2 complement discussion,

Binary arithmetic, Signed Magnitude, overflow, examples

Gray coding, Binary coded digital (BCD) coding, BCD addition

Digital logic gates basic (AND, OR, XOR, NOT) and derived (NAND, NOR and XNOR). Drive XOR from NAND gates. Drive XOR from NOR gates

Discussion of Boolean Algebra with examples.

Duality Principle, Huntington Postulates, Theorems of Boolean Algebra - discussion with examples, Boolean Functions, Canonical and Standard Forms, Minterms and Maxterms

Sum of Minterms, Product of Maxterms or Canonical Forms,

Karnaugh map or K-map discussion 2, 3, ,4 and 5 var’s

Prime Implicant and Gate level minimization examples.

Digital basics tutorial

Binary number discussion, 1 and 2 complement discussion,

Binary arithmetic, Signed Magnitude, overflow, examples

Gray coding, Binary coded digital (BCD) coding, BCD addition

Digital logic gates basic (AND, OR, XOR, NOT) and derived (NAND, NOR and XNOR). Drive XOR from NAND gates. Drive XOR from NOR gates

Discussion of Boolean Algebra with examples.

Duality Principle, Huntington Postulates, Theorems of Boolean Algebra -

Karnaugh map or K-

Prime Implicant and Gate level minimization examples.

Previous Next

case (r_count)

10 : begin

packet_in = 'haa;

wr_en = 'b1;

end

11 : begin

packet_in = 'hbb;

wr_en = 'b1;

end

12 : begin

packet_in = 'hcc;

wr_en = 'b1;

end

13 : begin

packet_in = 'hdd;

wr_en= 'b1;

end

endcase

Interview Questions. Main, FPGA, Digital Fundamentals

Solved 3 var K-map Examples

1. F(x,y,z) =sum(0,1,6,7) - Minimization.

2. F(x,y,z) =sum(0,1,4,5,6,7) - Minimization.

3. F(x,y,z) =sum(3,4,6,7) - Minimization.

4. F(x,y,z) =sum(0,1,2,3,4,5,6,7) - Minimization.

Four variable K-Map minimization example.

1. F(x,y,w, z) = (0,1,2,3,4,6,11,14)

2. F(x,y,w, z) = (0,2,4,6,12,14)

3. F(x,y,w, z) = (0,2,5,7,8,11,13,15)

2. F(x,y,w, z) = (0,2,4,6,12,14)

3. F(x,y,w, z) = (0,2,5,7,8,11,13,15)