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Initial statements with examples are discussed in this section. Also discussed are clocks and resets generation logic using forever loop and not operator.

Statements within initial block are used in Verilog for generating test signals, example clocks, resets etc.

Initial statements can’t be synthesized because actual behavior of hardware is difficult to model using fixed delays. These statements are used only for testbench purposes and to initialize the values at zero simulation time.

// Register declarations

reg clk_1fs;

reg clk_1fs_d;

reg rst_n;

// Use of initial statement to generate clocks 1fs and 1fs_d

initial begin

clk_1fs = 0;

clk_1fs_d = 0;

rst_n = 0;

#100 rst_n = 1;

forever begin

#10 clk_1fs = 1;

#11 clk_1fs_d = 1;

#10 clk_1fs = 0;

#11 clk_1fs_d = 0;

end end

end

reg clk;

reg rstn;

/* Initial block to generate clock and reset */

initial

begin

clk = 0; rstn = 0; #100 rstn = 1;

forever begin

#10 clk = !clk; end

end

reg rstn;

/* Initial block to generate clock and reset */

initial

begin

clk = 0; rstn = 0; #100 rstn = 1;

forever begin

#10 clk = !clk; end

end

Refer complete test-bench code with initial statements.

Some Examples below:-

Clocks and reset generation in test-bench using Initial statements.

Counter logic with enable disable logic generation using initial statements.

Verilog Initial Statements.

Resources

Verilog RTL code examples for front-end chip design.

Digital Design Topics

Half-adder , full-adder ,

Adder-sub tractor

Stack Organization - LIFO, RPN

Parity Generation and error checking

Binary multiplier circuit.

CMOS introduction

Digital fundamentals -

RTL coding guidelines. ICG cell, Assertions, $assertkill, levels. Chandle

Pipeline vs. Parallel processing.

Verilog RTL code examples for front-

Digital Design Topics

Half-

Adder-

Stack Organization -

Parity Generation and error checking

Binary multiplier circuit.

CMOS introduction

Digital fundamentals -

RTL coding guidelines. ICG cell, Assertions, $assertkill, levels. Chandle

Pipeline vs. Parallel processing.

Arithmetic, logical and shift microoperations.

Binary to Gray code conversion

Readmemh, Readmemb. Random numbers

Memory Implementation - sync Ram and Testbench

Binary to Gray code conversion

Readmemh, Readmemb. Random numbers

Memory Implementation -

Digital Logic fundamentals topics @ fcd

Digital basics tutorial

Binary number discussion, 1 and 2 complement discussion,

Binary arithmetic, Signed Magnitude, overflow, examples

Gray coding, Binary coded digital (BCD) coding, BCD addition

Digital logic gates basic (AND, OR, XOR, NOT) and derived (NAND, NOR and XNOR). Drive XOR from NAND gates. Drive XOR from NOR gates

Discussion of Boolean Algebra with examples.

Duality Principle, Huntington Postulates, Theorems of Boolean Algebra - discussion with examples, Boolean Functions, Canonical and Standard Forms, Minterms and Maxterms

Sum of Minterms, Product of Maxterms or Canonical Forms,

Karnaugh map or K-map discussion 2, 3, ,4 and 5 var’s

Prime Implicant and Gate level minimization examples.

Digital basics tutorial

Binary number discussion, 1 and 2 complement discussion,

Binary arithmetic, Signed Magnitude, overflow, examples

Gray coding, Binary coded digital (BCD) coding, BCD addition

Digital logic gates basic (AND, OR, XOR, NOT) and derived (NAND, NOR and XNOR). Drive XOR from NAND gates. Drive XOR from NOR gates

Discussion of Boolean Algebra with examples.

Duality Principle, Huntington Postulates, Theorems of Boolean Algebra -

Karnaugh map or K-

Prime Implicant and Gate level minimization examples.

Resources

Digital design resources

Clock Domain Crossing rtl & testbench.

Rate change (asynchronous) FIFO design and fifo depth calculation.

Half-adder , Full-adder , 4-bit binary adder , adder-subtractor circuit, overflow with rtl & testbench. Binary Multiplier, Parity error TT, Arithmetic, logical, shift micro-operations . Stack organization, LIFO, RPN discussion.

RTL coding guidelines. ICG cell, Assertions, $assertkill, levels.

Digital design Interview questions.

FPGA Interview. FPGA flow.

Guide to Graduate studies in US

Pipeline vs. Parallel processing.

Digital design resources

Clock Domain Crossing rtl & testbench.

Rate change (asynchronous) FIFO design and fifo depth calculation.

Half-

Digital design Interview questions.

FPGA Interview. FPGA flow.

Guide to Graduate studies in US

Pipeline vs. Parallel processing.

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Another example of initial statement to generate clock and reset using not operator.

LTE - Long Term Evolution topics from here