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initial
begin
 #0   X = 1; #0   Y = 2;  #0   Z = 0;
 #10 Z = X + Y;
end
initial
begin
 #0   X = 1;  #0   Y = 2; #0   Z = 0;
 Z =  #10 X + Y;
end
In the above example all three variables X, Y and Z will be initialized at time 0. The variable Z will get a sum of variables X and Y after delay of 10 time steps.
Behavioral modeling of hardware requires delay specifications. These delays are specified by using either inter statement or intra-statement delays.  The details are discussed below with reference to Verilog/SystemVerilog test-benches.
Intra statements delay control: This is an alternate technique of delay modeling by inserting delay as a part of statement execution. Lets review the above example with intra-statement delays.
In the above example # delay is moved inside the statement after ‘=’ sign. This method of coding will cause the value of X+Y to be stored in a temporary register for 10 time units. After that delay (10 time units) the register Z will get updated.  These are alternatively known as intra-assignments delay.
RTL Inter-statement and Intra-statement delay modeling
Inter-statement delay or normal delay control :- This is the most common approach of delay modeling in test-benches. In this technique a delay is inserted before or in-between statements . Above is an example of inter-statement delay.
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