﻿ Verilog Logical Shift Right microoperation code.
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Logical Shift micro-operations RTL

module shift_tb ();
reg clk, rst;
reg[7:0] x_q;
reg[7:0] x_d;
reg[4:0] q_cnt;

integer k, i;
integer out;
// Generate Clock
initial
begin
clk = 0;
forever #10 clk = ~clk;
end
// Release reset
initial begin
rst = 0;
# 50 rst = 1;
end
// Use positive edge of clock to shift the register value
// Implement logical right shift
always @(posedge clk or
negedge rst)
begin
if (!rst)
begin
x_q <= 'hed;
q_cnt <= 0;
out = \$fopen("shift_LR.vec","w");
end
else
begin
x_q <= x_d;
q_cnt <= q_cnt + 1;
\$fdisplay(out, "Pass %d Shift value in hex %b", q_cnt, x_q);
end
end
// shift logic
always @(*)
begin
x_d = x_q;
x_d[7] = 0;
for (i=0; i<7; i=i+1)
begin
x_d[i] = x_q[i+1];
end
end
endmodule
Verilog code for logical shift right microoperations.
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Circular Shift Right (CSR)
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In this section we will implement verilog code for shift micro-operations.
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