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Introduction Operators Initial stms Block vs. Non Blk IF-ELSE, CASE FORLOOP File Operations Read .bin format Function Call Testbench Random Numbers Shift Micro-ops Sync RAM Mem Generate Assertions Signed RTL
Verilog Tutorial.
Digital Basics Tutorial.
Category
Name
Symbol
Details
Logical
AND
&&
AND - True when all operands are TRUE
OR
||
OR - True when any one operand is TRUE
NOT
!
Not is like a inverter.
Logical - Operation on registers as logical statements True and false. These are primarily used in conditional statements like ‘IF’, ‘ELSE IF’
Category
Name
Symbol
Details
Comparison
Greater than
>
True when arithmetic value of one  register is greater than the other register in comparison.
Less than
<
True when arithmetic value of one  register is less than the other register in comparison.
Greater than or equal
>=
True when arithmetic value of one  register is greater than or equal to the other register in comparison.
Greater than or equal
<=
True when arithmetic value of one register is less than or equal to the other register.
Equal to
== or ===
‘==’ Logical equality excluding Tristate values (‘bX).
‘===’ Logical equality including Tristate values or ‘bX.
Not equal
!= or !==
‘!=’ Logical in-equality excluding Tristate values or ‘bX.
‘!==’ Logical in-equality including Tristate values or ‘bX.
Shift - Shift values of registers and store the new value.
Category
Name
Symbol
Details
Shift and store
Logical Right Shift
>>
Shift the contents of register right and drop the bits.
Logical Left Shift
<<
Shift the contents of register left and drop the bits.
Arithmetic Right Shift
>>>
Supported Verilog 2001 onwards. Shift the contents of register right and store the bits in MSB bits.
Arithmetic Left Shift
<<<
Supported Verilog 2001 onwards. Shift the contents of register left and store the bits in lsb bits.
Binary Aritmetic Operators - Each bit of the register is individually operated with corresponding bit in other register.  
Verilog Operators & digital logic fundamentals.
Category
Name
Symbol
Details
~
|
&
^
Bitwise - Operation on individual bits of registers. Also discussed is the verilog code implementation.
Category
Name
Symbol
Details
~&
~|
~^
^~
Others - conditionals, concatenation and replicate.
Category
Name
Symbol
Details
Concatenation
Concatenation
{ , }
Append two values in one register.
Example:- R3[5:0] = {R1[2:0],R2[2:0}
Replication
Replication
{r{p}}
Where value of p is replicated r times
Conditional
Conditional
(condition)? V1 : V2
If condition is true, assign value V1 else V2.
Introduction.
Initial stms.
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