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An assertion is a logical state defined to monitor the occurrence of certain events in the logic design during behavioural simulations. Defining logical states for assertions are implemented as properties (or rules). Each property can be visualized as a Boolean Expression.

As long as an assertion holds true no messages are populated in the logic simulation’s. Whenever assertions fails, simulator produces ‘Error messages’.
Types of Assertions:-
1) Immediate assertion.
2) Concurrent assertions.
Immediate Assertions -
Immediate assertions are executed only once and are mostly implemented within ‘initial blocks’. Due to limited use cases its not widely used and limited to simulations.

Example of immediate assertion below:-
assert (A==B) $display(“Pass”);
   else $error(“Fail, reporting Error”);

Failure of assertion is reported by else statement. In ‘else’ branch we can also include severity of the failure. The level of severity varies from $info, $warning, $error or $fatal. The $error is the default severity in SystemVerilog.
Concurrent Assertions -
The concurrent assertions are tied closely to the RTL design to behave inline with the implementation logic. These assertions are most valuable and widely used. Its useful for both formal verification and behavioral simulations.

There are two types of concurrent assertions :-
Assertions checking the property only with rising edges of the clock. Assertions which are always active in time and properties are constantly validated.
Assertions in Digital Logic Design - RTL (Verilog, SystemVerilog etc.)
Example of concurrent assertions:-
assert property (@posedge clk) (fifo_full && fifo_wr);

Checks that the FIFO full flag and FIFO write data control is never set high (or 1) at any rising edge of the clock.
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The two type of assertions are discussed in details with examples below.
LTE - Long Term Evolution topics.