﻿ Verilog case statements, finite state machine and counter examples
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Verilog Case construct.

Verilog “case” statements are used to model states in Finite State Machine.

Its also used to generate conditional statements based on value of a register. Case statement implementation is shown below in two examples below.

Next Check the counter code and the test bench example.

// Always block to generate synchronous packets in 1fs clock domain

// Implementing counters

always@(posedge clk_1fs or negedge rst_n)

begin

if (!rst_n) begin

r_count <= 'b0;  end

else begin

r_count <= count + 1 ; end

end

Synchronous Counter Example:
Counters are extensively used in synchronous RTL. In current implementation, its used for keeping track of packets. Check the complete usage of the counter code in the
Free running Verilog counters code with asynchronous reset and synchronous reset
Interview Questions. Main, FPGA, Digital Fundamentals
~\Desktop\verilog_code\casecode2.v.html
```        module casecode (
in_a,
in_b,
in_ctrl,
out_c
);
// Define inputs/outputs
input  in_a;
input  in_b;
input  in_ctrl;
output out_c;
// Use of case statement.
always@(*)
begin
case(in_ctrl)
1 : out_c = in_b;
default: out_c = in_a;
endcase
end
endmodule
```
>

Verilog case construct above is a simple multiplexor to select one of two inputs and assign it to output c.  Verilog 2001 onwards we can use * operator to list all variables of senstivity list of always block. Also note the use of default statement in verilog case is to avoid inferring of latches. The default statement ensures a known logic value for output at all unknown states.

LTE - Long Term Evolution topics from here

To handle ‘z’ and ‘x’ states, different variations of case statement  are used.

casez : Treats z as don't care.

casex : Treats x and z as don't care.

SystemVerilog case statement construct is similar to verilog.