Verilog code to Function call and Declaration. /*Verilog functions are discussed here.*/ reg [5:0] counter_binary, counter_binary_reg, counter_gray, counter_gray_reg; integer count, file_wr; /*Function Declaration: Gray from Binary code*/ function[5:0] binary2gray ; input[5:0] value; integer i; begin binary2gray = value; for (i=5; i>0; i = i - 1) binary2gray[i-1] = value[i] ^ value[i - 1]; end endfunction //Function call always @(*) begin counter_binary = counter_binary_reg; counter_gray = binary2gray(counter_binary_reg); end ............. endmodule Check the complete usage of the function in following verilog example
Verilog functions are used to simplify coding in presence of lengthy, complex and
repetitive code. Functions are used to group code segments which can then be used
multiple (no limit) times. Terms used in example code below are Function Declaration
and Function Call.
Properties of functions:
(1) Can only be used to pass one argument to/from function.
(2) Function code segments with latches will not get interpreted during synthesis.
So avoid latches in function code to prevent simulation/synthesis mis-match. (3)
A function can only be called from an “always” code block. For test benches its also
allowed from within “initial” blocks. (4) Never use delay, event or timing control
in functions. (5) Wires are not allowed in verilog functions.