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signal sig_write_data : std_logic;

begin

  Process (clk, rst)

    begin

         if (rst = '0') then

            sig_write_data <= '0';

         elsif (clk'event and clk = '1') then

             sig_write_data <= '1';

           else

             sig_write_data <= '0';

         end if;

   end process ;

end

Code that generates a synchronous latch in digital circuit and logic to correct it

Generation of latches in Digital Design should be avoided by correctly declaring all possible states in conditional statements.

architecture rtl of test is

signal sig_write_data : std_logic;

 begin

  Process (clk, rst)

      begin

         if (rst = '0') then

            sig_write_data <= '0';

         elsif (clk'event and clk = '1') then

            sig_write_data <= '1';

           end if;

   end process ;

end;

This latch code can be corrected or fixed by adding another else statement in the conditional if then else statement

Synchronous Flip - Flop and use of conditional statements in VHDL.

architecture rtl of test is

VHDL VHSIC (Very High Speed Integrated Circuit) Hardware Description Language.   

Following programs are discussed in this section