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Home Verilog Digital Design Digital Basics Python RF Basics
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Digital Basics Tutorial.

Program to implement synchronous counter in VHDL

library IEEE;

    use IEEE.std_logic_1164.all;

    use IEEE.std_logic_arith.all;

    use IEEE.std_logic_unsigned.all;

entity test is

    port (

        clk : in  STD_LOGIC;

        rst  : in  STD_LOGIC

            );

end;

architecture rtl of test is

signal sig_write_data : std_logic;

signal counter : std_logic_vector(3 downto 0);

begin

  Process (clk, rst)

      begin

         if (rst = '0') then

            counter <= "1111";

         elsif (clk'event and clk = '1') then

            counter <= counter + 1;           

         end if;

   end process ;

library IEEE;

    use IEEE.std_logic_1164.all;

    use IEEE.std_logic_arith.all;

    use IEEE.std_logic_unsigned.all;

entity test is 

    port ( 

        clk : in  STD_LOGIC;

        rst  : in  STD_LOGIC;

        wrdata_in  : in  STD_LOGIC;

        wrdata_out : out  STD_LOGIC

           ); 

end; 

architecture rtl of test is 

  signal sig_write_data : std_logic;

  begin

  Process (clk, rst)

     begin

         if (rst = '0') then 

            sig_write_data <= '0'; 

         elsif (clk'event and clk = '1') then

            sig_write_data <= wrdata_in;    

         end if;

  end process ; 

  wrdata_out <= sig_write_data;

end; 

 

 

Program to implement a shim to register data. Logic to improve timing in digital circuits.
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