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Here you will find over 250 Pages on various topics that are  essential to become a Digital Design and/or verification engineer. Start exploring the content through Navigation Bars on this page. Some suggestions below
Verilog RTL code examples for front-end chip design.
RTL coding guidelines. ICG cell, Assertions, $assertkill, levels. Chandle
Pipeline vs. Parallel processing.
Digital logic fundamentals.
Digital Design Topics. Like ...Half-adder, full-adder, Adder-sub tractor Interrupt cntr VIC’s. Interrupt registers
Stack Organization - LIFO, RPN, Parity Generation and error checking, Binary multiplier circuit.
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Static Timing Analysis

Setup time and hold time in digital circuits? Hint : Access from here False path in FPGA’s, Critical path, Negative slack, Jitter vs. clock skew. Routing delay, Flop to out delay, Flop to flop delay, Pad to flop delay, Board delay. Knowledge of Synthesis and layout constraints.

Digital Logic fundamentals topics @ fcd tutorial

Binary number discussion, 1 and 2 complement discussion, Binary arithmetic, Signed Magnitude, overflow, examples Gray coding, Binary coded digital (BCD) coding, BCD addition. Digital logic gates basic (AND, OR, XOR, NOT) and derived (NAND, NOR and XNOR). Drive XOR from NAND gates. Drive XOR from NOR gates Discussion of Boolean Algebra with examples. Duality Principle, Huntington Postulates, Theorems of Boolean Algebra - discussion with examples, Boolean Functions, Canonical and Standard Forms, Minterms and Maxterms Sum of Minterms, Product of Maxterms or Canonical Forms, Karnaugh map or K-map discussion 2, 3, ,4 5 var’s Prime Implicant and Gate level minimization examples.