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Chip Designing for ASIC/ FPGA Design engineers and Students

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Digital-logic Design... Dream for many students… start learning front-end…

Clock domain crossing discussion.

Setup time, hold time and metastability

Asynchronous FIFO design and depth calculation.

Half-adder discussion with circuit and truth-table.

Full-adder discussion with circuit and truth table.

4 bit binary adder circuit and examples.

Setup time, hold time and metastability

Asynchronous FIFO design and depth calculation.

Half-

Full-

4 bit binary adder circuit and examples.

Overflow in Binary Arithmetic scenarios.

Overflow in signed magnitude with examples.

Binary adder-subtractor circuit with examples.

Binary multiplier circuit and discussion.

Parity generation and check,error, Truth Table

RTL coding guidelines for digital hardware design.

NAND to inverter conversion (two methods).

VHDL RTL discussion (in short) with examples.

Program to implement synchronous flip flop and use of conditional statements in VHDL.

Code to generate a synchronous latch and logic to correct it in design.

Use of flip-flops in a shim to register data. Generally this logic is implemented in FPGA’s to improve timing.

Program to implement synchronous counter.

Overflow in signed magnitude with examples.

Binary adder-

Binary multiplier circuit and discussion.

Parity generation and check,error, Truth Table

RTL coding guidelines for digital hardware design.

NAND to inverter conversion (two methods).

VHDL RTL discussion (in short) with examples.

Program to implement synchronous flip flop and use of conditional statements in VHDL.

Code to generate a synchronous latch and logic to correct it in design.

Use of flip-

Introduction to Verilog RTL

Verilog Operators.

Initial Statements in verilog.

Clock and Reset generation.

Blocking vs. Non-blocking Statements.

Conditional Statements & ‘always’ block.

Counter Implementation.

File Operations - $fopen, $fclose, $fdisplay, $fscanf

Read binary or hex format files - $readmemh, $readmemb.

FOR Loop use in verilog code example

Verilog Operators.

Initial Statements in verilog.

Clock and Reset generation.

Blocking vs. Non-

Conditional Statements & ‘always’ block.

Counter Implementation.

File Operations -

Read binary or hex format files -

FOR Loop use in verilog code example

Digital Logic fundamentals topics @ fcd

Digital basics tutorial

Binary number discussion, 1 and 2 complement discussion,

Binary arithmetic, Signed Magnitude, overflow, examples

Gray coding, Binary coded digital (BCD) coding, BCD addition

Digital logic gates basic (AND, OR, XOR, NOT) and derived (NAND, NOR and XNOR). Drive XOR from NAND gates. Drive XOR from NOR gates

Discussion of Boolean Algebra with examples.

Duality Principle, Huntington Postulates, Theorems of Boolean Algebra - discussion with examples,

Boolean Functions,

Canonical and Standard Forms, Minterms and Maxterms

Sum of Minterms, Product of Maxterms or Canonical Forms,

Karnaugh map or K-map discussion 2, 3, ,4 and 5 var’s

Prime Implicant and Gate level minimization examples.

Digital basics tutorial

Binary number discussion, 1 and 2 complement discussion,

Binary arithmetic, Signed Magnitude, overflow, examples

Gray coding, Binary coded digital (BCD) coding, BCD addition

Digital logic gates basic (AND, OR, XOR, NOT) and derived (NAND, NOR and XNOR). Drive XOR from NAND gates. Drive XOR from NOR gates

Discussion of Boolean Algebra with examples.

Duality Principle, Huntington Postulates, Theorems of Boolean Algebra -

Canonical and Standard Forms, Minterms and Maxterms

Sum of Minterms, Product of Maxterms or Canonical Forms,

Karnaugh map or K-

Prime Implicant and Gate level minimization examples.

Evolved Packet Core (EPC) system architecture for all IP.Mobility Management Entity (MME),

Serving System (S) Architecture (A) Evolution (E) Gateway or Serving Gateway SGW.

Packet Data Network (PDN) SAE Gateway

Enhanced Packet Data Gateway (ePDG)

Multiple antenna techniques -

MIMO, Adaptive antenna systems - AAS and

Antenna diversity - AD

Serving System (S) Architecture (A) Evolution (E) Gateway or Serving Gateway SGW.

Packet Data Network (PDN) SAE Gateway

Enhanced Packet Data Gateway (ePDG)

Multiple antenna techniques -

Return to Verilog Tutorial

Interview Questions. Main, FPGA, Digital Fundamentals

Resources

Digital design resources

Clock Domain Crossing rtl & testbench.

Rate change (asynchronous) FIFO design and fifo depth calculation.

Half-adder , Full-adder , 4-bit binary adder , adder-subtractor circuit, overflow with rtl & testbench. Binary Multiplier, Parity error TT, Arithmetic, logical, shift micro-operations . Stack organization, LIFO, RPN discussion.

RTL coding guidelines. ICG cell, Assertions, levels.

Digital design Interview questions.

FPGA Interview. FPGA flow.

Guide to Graduate studies in US

Pipeline vs. Parallel processing.

Digital design resources

Clock Domain Crossing rtl & testbench.

Rate change (asynchronous) FIFO design and fifo depth calculation.

Half-

Digital design Interview questions.

FPGA Interview. FPGA flow.

Guide to Graduate studies in US

Pipeline vs. Parallel processing.

Arithmetic, logical and shift microoperations.

Binary to Gray code conversion

Readmemh, Readmemb. Random numbers

Memory Implementation sync Ram and Testbench

Binary to Gray code conversion

Readmemh, Readmemb. Random numbers

Memory Implementation sync Ram and Testbench