Digital design Synthesis for VLSI applications: Its a EDA technique to map high
level behavioral designs into gates. Behavioral designs are coded in Register Transfer
Level languages like Verilog, VHDL etc.
The synthesized gates are distributed over an assigned area and are connected with
wires. This synthesized gate level abstraction or net list is then optimized in several
steps to attain faster speed, low area, low power and test-ability.
Flowchart below shows the different stages of digital synthesis for ASIC’s/FPGA’s.
Read in Technology library
Read in RTL behavioural design
Read in design constraints
Synthesis: Pre-possessing of the design. (Syntax check, compile and elaboration.)
Logic minimization and optimization in terms of Boolean Logic.
Mapping of minimized logic to technology library elements.
Post processing of Mapped design. (Constraint validation and re-optimization)
Net-list (Structural Design)
VLSI Synthesis for Digital Logic
When its appropriate to take RTL through Synthesis?
The design is ready for synthesis when its functional behavior is well understood
in code and it simulates without any issues. Feedback from synthesis reports helps
in clearing out issues in code and it also helps in code optimization.