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Boolean Algebra

This property of Boolean algebra state that all binary expressions remain valid when following two steps are performed:

Step 1: Interchange OR and AND operators.

Step 2: Replace all 1’s by 0’s and 0’s by 1’s.

Adding a number to ‘0’

P1. Postulate:-

From duality of P1

P2. Postulate:-

Sum of a number and its complement from a Set is ‘1’.

P3. Postulate:-

From duality of P3

P4. Postulate:-

From commutative property of binary numbers we have:-

P5. Postulate:-

From duality of P5

P6. Postulate:-

From distributive property of binary numbers we have:-

P7. Postulate:-

From duality of P7

P8. Postulate:x + y = (x + y) (x + z)

T1. Theorem:-

x + x = (x + x)*1= (x + x)(x + x’)

From P8, x + xx’ = x

From duality of T1

T2. Theorem:-

T3. Theorem:-

x + 1= (x + 1).1= (x +1)*(x + x’)

From P8, (x + 1*x’)= (x + x’)= 1

From duality of T3

T4. Theorem:-

T5. x + (y + z) = (x + y) + z

From duality of T5

T6. Theorem:-

T7. Theorem:-

From duality of T10

T11. Theorem:-

T8. Theorem:-

T9. Theorem:-

T10. Theorem:-

Resources

Verilog RTL code examples for front-end chip design.

Digital Design Topics

Half-adder , full-adder ,

Adder-sub tractor

Stack Organization - LIFO, RPN

Parity Generation and error checking

Binary multiplier circuit.

CMOS introduction

Digital fundamentals -

RTL coding guidelines. ICG cell, Assertions, $assertkill, levels. Chandle

Pipeline vs. Parallel processing.

Verilog RTL code examples for front-

Half-

Adder-

Stack Organization -

Binary multiplier circuit.

CMOS introduction

Digital fundamentals -

RTL coding guidelines. ICG cell, Assertions, $assertkill, levels. Chandle

Pipeline vs. Parallel processing.

Computer Organization.

Computer Introduction. Building blocks - ALU, ACC, PC, Registers, Stack Pointer, IR, timing and control unit.

Memory Organization.

Cache memory, fully-associative cache , hardware architecture, match circuit, control circuit. Direct-mapped cache , main memory and discussion.

Interrupt controller, Vectored Interrupt Controller. Interrupt registers

Computer Introduction. Building blocks -

Memory Organization.

Cache memory, fully-

Interrupt controller, Vectored Interrupt Controller. Interrupt registers

LTE - Long Term Evolution topics1 here.

Interview Questions. Main, FPGA, Digital Fundamentals