Chip Designing for ASIC/ FPGA Design engineers and Students
Digital-logic Design... Dream for many students… start learning front-end…
For components like op-amps, we specify noise in terms of equivalent voltages and current. But at system level its difficult to account for noise contributions of each component in each sub-system. Instead we use another term widely know as Noise Factor (F) of a sub-system.
Block Diagram - Noise contributions
Block Diagram: N access noise contributions at the input of system.
Rest of our calculations are based on the equivalent noise Factor of the system with cascaded components. In order to calculate total noise factor, we will need to refer the noise back at the input of the system. Block diagram below shows the Total Noise contributions.
Total noise factor at the input of the system is calculated with formula below:
Total Noise Factor of cascaded system with 3 blocks is below
Ftotal = F1+(F2-1)/G1+ (F3-1)/(G1G2)
LTE - Long Term Evolution topics
Digital Logic fundamentals topics @ fcd
Digital basics tutorial
Binary number discussion, 1 and 2 complement discussion, Binary arithmetic, Signed Magnitude, overflow, examples, Gray coding, Binary coded digital (BCD) coding, BCD addition
Digital logic gates basic (AND, OR, XOR, NOT) and derived (NAND, NOR and XNOR). Drive XOR from NAND gates. Drive XOR from NOR gates, Discussion of Boolean Algebra with examples.
Duality Principle, Huntington Postulates, Theorems of Boolean Algebra - discussion with examples, Boolean Functions, Canonical and Standard Forms, Minterms and Maxterms, Sum of Minterms, Product of Maxterms or Canonical Forms, Karnaugh map or K-map discussion 2, 3, ,4 and 5 var’s, Prime Implicant and Gate level minimization examples.
Clock Domain Crossing Discussion with
rtl & testbench example.
Rate change(asynchronous) FIFO design and fifo depth calculation.
Half-adder, Full-adder, 4-bit binary adder , adder-subtractor circuit, overflow with rtl & testbench. Binary Multiplier, Parity error TT
Arithmetic, logical, shift micro-operations. Stack organization, LIFO, RPN discussion.
VHDL rtl - Synchronous flip-flop, latch, shim to improve timing and counter example
RTL coding guidelines. ICG cell, Assertions, levels.
Digital design Interview questions.
FPGA Interview. FPGA flow.
Guide to Graduate studies in US
Pipeline vs. Parallel processing.
SNR = Signal Power / Noise Power
In above diagram, we have noise contributions by each sub-block as (Fn-1)kTB.
Sub block has gains G1, G2 and G3.
Sub-block has individual noise contribution as F1, F2 and F3.
k is Boltzman constant,
T is temperature (degrees Kelvin) and
B is frequency bandwidth (in Hz).