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Digital Basics Tutorial.
Parity Generation and Checking
In digital communications, a large amount of data is transmitted and received across various mediums. Mostly during the transfers some noise gets added to the data and makes it difficult to recover signal.
To Make the data recovery easier an extra bit is appended to the binary (0,1) message to make the ‘logic 1’ count even or odd. This extra bit is known as parity bit and used for error detection.
The block diagram implementation of generator and checker shows that the circuit requires 2 XOR gates at the parity generation side of transmitter and 3 XOR gates at the receiver side of parity checker.
Discussion of parity generation and checker circuit below
Circuit Level implementation of parity generator and parity checker.
Parity systems are implemented on both transmitters and receivers. The transmitter is responsible for generating the parity bit. The receiver is responsible for detecting the message including the parity bit. If message doesn’t meet the parity check an error flag is generated and transmitter is requested to re-transmit the packet.
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