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Circular shift micro-operations.

In this shift operation the MSB bit of the register are virtually connected to the LSB bit of the same register. So in case of shift operation (left or right) the data does not get lost. Instead the data moves in a circular fashion.

Refer Arithmetic shift micro-operation from here.

In this shift operation the MSB bit of the register are virtually connected to the LSB bit of the same register. So in case of shift operation (left or right) the data does not get lost. Instead the data moves in a circular fashion.

Refer Arithmetic shift micro-

1 |
0 |
0 |
1 |

0

0 |
0 |
1 |
0 |

Links to all microoperations discussion:-

Arithmetic microoperations discussion,

Logical microoperations discussion,

Shift microoperations discussion,

Overflow conditions and discussion.

Arithmetic microoperations discussion,

Logical microoperations discussion,

Shift microoperations discussion,

Overflow conditions and discussion.

Shift micro operations are involved in shifting of bits of a register. These operations are categorized into three groups.

Logical shift micro-operation: In these operations bit streams of 0 are used to fill in vacated bits.

Circular Shift micro-operation.

Arithmetic shift micro-operation.

Detailed discussion below

Logical shift micro-

Circular Shift micro-

Arithmetic shift micro-

Detailed discussion below

So after left shift 1 the content of register A will be

Verilog code examples for shift micro-operations are at links below:-

Logical Shift Right (LSR) verilog code,

Logical Shift left (LSL) verilog code,

Circular Shift Right (CSR) verilog code,

Circular Shift Left (CSL). Verilog code.

Logical Shift Right (LSR) verilog code,

Logical Shift left (LSL) verilog code,

Circular Shift Right (CSR) verilog code,

Circular Shift Left (CSL). Verilog code.

So an example of shift left microoperations on register A = 1001 is shown below: (Reverse of below will give shift right)

Interview Questions. Main, FPGA, Digital Fundamentals

Resources

Verilog RTL code examples for front-end chip design.

Digital Design Topics

Half-adder , full-adder ,

Adder-sub tractor

Stack Organization - LIFO, RPN

Parity Generation and error checking

Binary multiplier circuit.

CMOS introduction

Digital fundamentals -

RTL coding guidelines. ICG cell, Assertions, $assertkill, levels. Chandle

Pipeline vs. Parallel processing.

Verilog RTL code examples for front-

Digital Design Topics

Half-

Adder-

Stack Organization -

Parity Generation and error checking

Binary multiplier circuit.

CMOS introduction

Digital fundamentals -

RTL coding guidelines. ICG cell, Assertions, $assertkill, levels. Chandle

Pipeline vs. Parallel processing.

LTE - Long Term Evolution topics from here