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ICG cell Assertions Concise assert Assert levels Chandle defparam Parameters Parameters Pass Defparam stms Localparam Constant Pass Alias Array Functions always
Verilog Tutorial.
Digital Basics Tutorial.
Verilog Parameters and defparam statements.
To understand verilog defparam statements we will need to understand parameters first.. Lets discuss modular coding style, parameters and defparam statements here.
What is modular coding style?
Its a style of writing Verilog code where a block of code can be re-used multiple times without making any modification. This reuse sometimes requires blocks of different widths to store and process signals of different widths or depths ( for memory).

What are verilog parameters?
The parameters in verilog is a way of passing the constants to modules so as to overwrite there local constants for signal widths and depths (for memories).  This is done when the block is instantiated in top-level/higher-level module.
Refer parameters use example on next page.
Code snippet from the sync ram page is shown below:
module mem_ram_sync(
   clk,
   rst,
   read_rq,
   write_rq,
   rw_address,
   write_data,
   read_data);
input             clk;
input             rst;
input             read_rq;
input             write_rq;
input[5:0] rw_address;
input[7:0]  write_data;
output[7:0] read_data;
reg[7:0]     read_data;
integer out, i;
// Declare memory 64x8 bits = 512 bits or 64 bytes
/* Width of memory 8 bits and Depth of memory 64 locations */
reg [7:0] memory_ram_d [63:0];
reg [7:0] memory_ram_q [63:0];
// Code from here refer sync ram page
......
......
......
endmodule

In this code no parameters are used. Lets modify the highlighted code to use parameters.
What are verilog defparam statements?
These statements provide alternate method of assigning new values to parameters inside sub-level modules. Example to use parameter & defparam statement is discussed here.
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